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machxo2? family data sheet advance ds1035 version 01.0, november 2010
www.latticesemi.com 1-1 ds1035 introduction_01.0 november 2010 advance data sheet ds1035 ? 2010 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. features ? flexible logic architecture ? six devices with 256 to 6864 lut4s and ? 18 to 335 i/os ? ultra low power devices ? advanced 65 nm low power process ? as low as 19 w standby power ? programmable low swing differential i/os ? stand-by mode and other power saving options ? embedded and distributed memory ? up to 240 kbits sysmem? embedded block ram ? up to 54 kbits distributed ram ? dedicated fifo control logic ? on-chip user flash memory ? up to 256 kbits of user flash memory ? 100,000 write cycles ? accessible through wishbone, spi, i 2 c and jtag interfaces ? can be used as soft processor prom or as flash memory ? pre-engineered source synchronous i/o ? ddr registers in i/o cells ? dedicated gearing logic ? 7:1 gearing for display i/os ? generic ddr, ddrx2, ddrx4 ? dedicated ddr/ddr2/lpddr memory with dqs support ? high performance, flexible i/o buffer ? programmable sysio? buffer supports wide range of interfaces: ? lvcmos 3.3/2.5/1.8/1.5/1.2 ? lvttl ?pci ? lvds, bus-lvds, mlvds, rsds, lvpecl ? sstl 25/18 ? hstl 18 ? schmitt trigger inputs, up to 0.5v hysteresis ? i/os support hot socketing ? on-chip differential termination ? programmable pull-up or pull-down mode ? flexible on-chip clocking ? eight primary clocks ? up to two edge clocks per edge for high-speed ? i/o interfaces ? up to two analog plls per device with ? fractional-n frequency synthesis ? wide input frequency range (10 mhz to ? 400 mhz) ? non-volatile, infinitely reconfigurable ? instant-on ? powers up in microseconds ? single-chip, secure solution ? programmable through jtag, spi or i 2 c ? supports background programming of non-vola- tile memory ? optional dual boot with external spi memory ? transfr? reconfiguration ? in-field logic update while system operates ? enhanced system level support ? on-chip hardened functions: spi, i 2 c, timer/ counter ? on-chip oscillator with 5% accuracy ? unique traceid for system tracking ? one time programmable (otp) mode ? single power supply with extended operating range ? ieee standard 1149.1 boundary scan ? ieee 1532 compliant in-system programming ? broad range of package options ? tqfp, wlcsp, ucbga, csbga, cabga, ftbga, fpbga package options ? small footprint package options ? as small as 2.5x2.5mm ? density migration supported ? advanced halogen-free packaging machxo2 family data sheet introduction
1-2 introduction lattice semiconductor machxo 2 family data sheet table 1-1. machxo2? family selection guide introduction the machxo2 family of ultra low power, instant-on, non-vo latile plds has six devices with densities ranging from 256 to 6864 look-up tables (luts). in addition to lut-based, low-cost programmable logic these devices feature embedded block ram (ebr), distributed ram, user flash memory (ufm), phase locked loops (plls), pre- engineered source synchronous i/o s upport, advanced configur ation support including dual-boot capability and hardened versions of commonly used functions such as spi controller, i 2 c controller and timer/counter. these fea- tures allow these devices to be used in low cost, high volume consumer and system applications. the machxo2 devices are designed on a 65nm non-volatile low power process. the device architecture has sev- eral features such as programmable low swing differential i/os and th e ability to turn off i/o banks, on-chip plls and oscillators dynamically. these feat ures help manage static and dynamic power consumption resulting in low microwatt static power for all members of the family. the machxo2 devices are available in two versions ? ultra low power (ze) and high performance (hc and he) devices. the ultra low power devices are offered in three speed grades -1, -2 and -3, with -3 being the fastest. sim- ilarly, the high-performance devices are offered in three speed grades: -4, -5 and -6, with -6 being the fastest. hc devices have an internal linear voltage regulator which supports external vcc supply voltages of 3.3v or 2.5v. ze device lcmxo2-256 lcmxo2-640 lcmxo2-1200 lcmxo2-2000 lcmxo2-4000 lcmxo2-7000 4 6 8 6 0 2 3 4 2 1 1 2 0 8 2 1 0 4 6 6 5 2 s t u l distributed ram (kbits) ebr sram (kbits) number of ebr sram blocks (9 kbits/block) 02781026 ufm memory bits (kbits) 0 24 64 80 96 256 v cc voltage and device options low power without regulator (ze) ?1.2v high performance with regulator (hc) ?2.5v, 3.3v low power without regulator (ze) ?1.2v high performance with regulator (hc) 2.5v, 3.3v high performance without regulator (he) ?1.2v number of plls 0 0 1 1 2 2 hardened functions: i 2 c spi timer/counter 2 1 1 2 1 1 2 1 1 2 1 1 2 1 1 2 1 1 2 5 10 16 34 54 0 18 64 74 92 240 s o / i s e g a k c a p 100-pin tqfp (14x14 mm, 0.5 mm) 144-pin tqfp (20x20 mm, 0.5 mm) 64-ball ucbga (4x4 mm, 0.4 mm) 45 132-ball csbga (8x8 mm, 0.5 mm) 256-ball cabga (14x14 mm, 0.8 mm) 256-ball ftbga (17x17 mm, 1.0 mm) 332-ball cabga notes: common footprint allows density migration within the same package. 1. contact your lattice sales representative for the support of wlcsp packages. (17x17 mm, 0.8 mm) 484-ball fpbga (23x23 mm, 1.0 mm) 25-ball wlcsp 1 (2.5x2.5 mm, 0.4 mm) 36-ball wlcsp 1 (3.1x3.1 mm, 0.4 mm) 56 79 80 80 56 80 105 105 105 207 207 207 207 29 18 207 207 275 279 279 335 108 112 115 115
1-3 introduction lattice semiconductor machxo 2 family data sheet and he devices only accept 1.2v as the external v cc supply voltage. with the exception of power supply voltage all three types of devices (ze, hc and he) are functionally compatible and pin compatible with each other. the machxo2 plds are available in a broad range of advanced halogen-free packages ranging from the space saving 2.5x2.5 mm wlcsp to the 23x23 mm fpbga. machxo2 devices support density migration within the same package. table 1-1 shows the lut densities, package and i/o options, along with other key parameters. the pre-engineered source synchronous logic implemented in the machxo2 device family supports a broad range of interface standards, incl uding lpddr, ddr, ddr2 and 7: 1 gearing for display i/os. the machxo2 devices offer enhanced i/o features such as drive strength control, slew rate control, pci compati- bility, bus-keeper latches, pu ll-up resistors, pull-down re sistors, open drain outputs and hot socketing. pull-up, pull- down and bus-keeper features are controllable on a ?per-pin? basis. a user-programmable internal oscillator is included in machxo2 devices. the clock output from this oscillator may be divided by the timer/counter for use as clock input in functions such as led control, key-board scanner and sim- ilar state machines. the machxo2 devices also provide flexible, reliable and secure configuration from on-chip flash memory. these devices can also configure themselves from external spi fl ash or be configured by an external master through the jtag test access po rt or through the i 2 c port. additionally, machxo2 devices support dual-boot capability (using external flash memory) and remote field upgrade (transfr) capability. lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the machxo2 family of devices. popular logic synthesis tools provide synthesis library support for machxo2. lattice design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route the design in the machxo2 device. these tools extract the timing from the routing and back-annotate it into the design for timing verification. lattice provides many pre-engineered ip (intellectual pr operty) latticecore? modules, including a number of reference designs licensed free of charge, optimized for the machxo2 pld family. by using these configurable soft core ip cores as standardized blocks, users are free to concentrate on the unique aspects of their design, increas- ing their productivity.
www.latticesemi.com 2-1 ds1035 architecture_01.0 november 2010 advance data sheet ds1035 ? 2010 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. architecture overview the machxo2 family architecture contains an array of logic blocks surrounded by programmable i/o (pio). the larger logic density devices in this family have sys clock? plls and blocks of sysmem embedded block ram (ebrs). figures 2-1 and 2-2 show the block diagrams of the various family members. figure 2-1. top view of the machxo2-1200 device figure 2-2. top view of the machxo2-4000 device sysmem embedded block ram (ebr) sysclock pll pios arranged into sysio banks programmable function units with distributed ram (pfus) embedded function block (efb) user flash memory (ufm) on-chip configuration flash memory note: 1. machxo2-256, and machxo2-640 are similar to machxo2-1200. both devices have no plls. machxo2-256 has a lower lut count and no ebr blocks. machxo2-640 has a lower lut count and two ebr blocks. sysmem embedded block ram (ebr) programmable function units with distributed ram (pfus) on-chip configuration flash memory sysclock pll pios arranged into sysio banks embedded function block(efb) user flash memory (ufm) note: machxo2-2000 and machxo2-7000 are similar to machxo2-4000. machxo2-2000 has a lower lut count, one pll, and eight ebr blo cks. machxo2-7000 has a higher lut count, two plls, and 24 ebr blocks. machxo2 family data sheet architecture
2-2 architecture lattice semiconductor machxo 2 family data sheet the logic blocks, programmable functional unit (pfu) and sysmem ebr blocks, are arranged in a two-dimen- sional grid with rows and columns. each row has either the logic blocks or the ebr blocks. the pio cells are located at the periphery of the device, arranged into banks. the pfu contains the building blocks for logic, arithme- tic, ram, rom, and register functions. the pios utilize a flexible i/o buff er referred to as a sysio buffer that sup- ports operation with a variety of interface standards. the blocks are connected with many vertical and horizontal routing channel resources. the place and route software tool automatically allocates these routing resources. in the machxo2 family, the number of sysio banks varies by device. there are different types of i/o buffers on the different banks. refer to the details in later sections of this document. the sysmem ebrs are large, dedicated fast memory blocks; these blocks are found in machxo2-640 and larger devices. these blocks can be configured as ram, rom or fifo. fifo support includes dedicated fifo pointer and flag ?hard? control logic to minimize lut usage. the machxo2 architecture also provides up to two sysclock phase locked loop (pll) blocks on machxo2- 1200 and larger devices. these blocks are located at the ends of the on-chip flash block. the plls have multiply, divide, and phase shifting capabilities that are used to manage th e frequency and phase rela tionships of the clocks. machxo2 devices provide commonly used hardened functions such as spi controller, i 2 c controller and timer/ counter. machxo2-640 and higher density devices also provide user flash memory (ufm). these hardened func- tions and the ufm interface to the core logic and routing through a wishbone interface. the ufm can also be accessed through the spi, i 2 c and jtag ports. every device in the family has a jtag port that supports programming and configuration of the device as well as access to the user logic. the machxo2 devices are available for operation from 3.3v, 2.5v and 1.2v power sup- plies, providing easy integration into the overall system. pfu blocks the core of the machxo2 device consists of pfu blocks , which can be programmed to perform logic, arithmetic, distributed ram and distributed rom functions. each pfu bloc k consists of four interconnected slices numbered 0 to 3 as shown in figure 2-3. each slice contains two luts and two registers. there are 53 inputs and 25 outputs associated with each pfu block. figure 2-3. pfu block diagram slice 0 lut4 & carry lut4 & carry ff/ latch fcin fco d ff/ latch d slice 1 lut4 & carry lut4 & carry slice 2 lut4 & carry lut4 & carry from routin g to routin g slice 3 lut4 & carry lut4 & carry ff/ latch d ff/ latch d ff/ latch d ff/ latch d ff/ latch d ff/ latch d
2-3 architecture lattice semiconductor machxo 2 family data sheet slices slices 0-3 contain two lut4s feeding two registers. slices 0-2 can be configured as distributed memory. table 2-1 shows the capability of the s lices in pfu blocks along wit h the operation mode s they enable. in addition, each pfu contains logic that allows the luts to be combined to perform functions such as lut5, lut6, lut7 and lut8. the control logic performs set/reset functions (programma ble as synchronous/ asynchr onous), clock select, chip- select and wider ram/rom functions. table 2-1. resources and modes available per slice figure 2-4 shows an overview of the internal logic of the slice. the registers in the slice can be configured for posi- tive/negative and edge triggered or level sensitive clocks. all slices have 15 inputs from routing and one from the carry-chain (from the adjacent slice or pfu). there are seven outputs: six for routing and one to carry-chain (to the adjacent pfu). table 2-2 lists the signals associated with slices 0-3. figure 2-4. slice diagram slice pfu block resources modes slice 0 2 lut4s and 2 registers logic, ripple, ram, rom slice 1 2 lut4s and 2 registers logic, ripple, ram, rom slice 2 2 lut4s and 2 registers logic, ripple, ram, rom slice 3 2 lut4s and 2 registers logic, ripple, rom lut4 & carry slice ff/ latch ofx0 f0 q0 ci co lut4 & carry ci co ofx1 f1 q1 f/sum f/sum d d fci from different slice/pfu fco to different slice/pfu lut5 mux from routing to routing for slices 0 and 1, memory control signals are generated from slice 2 as follows: wck is clk wre is from lsr di[3:2] for slice 1 and di[1:0] for slice 0 data from slice 2 wad [a:d] is a 4-bit address from slice 2 lut input a0 c0 d0 a1 b1 c1 d1 ce clk lsr m1 m0 fxb fxa b0 ff/ latch
2-4 architecture lattice semiconductor machxo 2 family data sheet table 2-2. slice signal descriptions modes of operation each slice has up to four potential modes of operation: logic, ripple, ram and rom. logic mode in this mode, the luts in each slice are configured as 4-input combinatorial lookup tables. a lut4 can have 16 possible input combinations. any four input logic functions can be generated by programming this lookup table. since there are two lut4s per slice, a lut5 can be cons tructed within one slice. larger look-up tables such as lut6, lut7 and lut8 can be constructed by concatenatin g other slices. note lut8 requires more than four slices. ripple mode ripple mode supports the efficient implementation of small arithmetic functions. in ripple mode, the following func- tions can be implemented by each slice: ? addition 2-bit ? subtraction 2-bit ? add/subtract 2-bit using dynamic control ? up counter 2-bit ? down counter 2-bit ? up/down counter with asynchronous clear ? up/down counter with preload (sync) ? ripple mode multiplier building block ? multiplier support ? comparator functions of a and b inputs ? a greater-than-or-equal-to b ? a not-equal-to b ? a less-than-or-equal-to b function type signal names description input data signal a0, b0, c0, d0 inputs to lut4 input data signal a1, b1, c1, d1 inputs to lut4 input multi-purpose m0/m1 multi-purpose input input control signal ce clock enable input control signal lsr local set/reset input control signal clk system clock input inter-pfu signal fcin fast carry in 1 output data signals f0, f1 lut4 output register bypass signals output data signals q0, q1 register outputs output data signals ofx0 output of a lut5 mux output data signals ofx1 output of a lut6, lut7, lut8 2 mux depending on the slice output inter-pfu signal fco fast carry out 1 1. see figure 2-3 for connection details. 2. requires two pfus.
2-5 architecture lattice semiconductor machxo 2 family data sheet ripple mode includes an optional configuration that performs arithmetic using fast carry chain methods. in this con- figuration (also referred to as ccu2 mode) two additional signals, carry generate and carry propagate, are gener- ated on a per-slice basis to allow fast arithmetic fu nctions to be constructed by concatenating slices. ram mode in this mode, a 16x4-bit distributed single port ram (spr ) can be constructed by using each lut block in slice 0 and slice 1 as a 16x1-bit memory. slice 2 is used to provide memory address and control signals. a 16x2-bit pseudo dual port ram (pdpr) memory is created by usin g one slice as the read-write port and the other compan- ion slice as the read-only port. machxo2 devices support distri buted memory initialization. the lattice design tools support the creation of a variety of different size memories. where appropriate, the soft- ware will construct these using distribute d memory primitives that represent th e capabilities of the pfu. table 2-3 shows the number of slices required to implement different distributed ram primitives. for more information about using ram in machxo2 devices, please see tn1201, memory usage guide for machxo2 devices . table 2-3. number of slices required for implementing distributed ram rom mode rom mode uses the lut logic; hence, slices 0-3 can be used in rom mode. preloading is accomplished through the programming interface during pfu configuration. for more information on the ram and rom modes, please refer to tn1201, memory usage guide for machxo2 devices . routing there are many resources provided in the machxo2 devices to route signals individually or as buses with related control signals. the routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg- ments. the inter-pfu connections are made with three different types of routing resources: x1 (spans two pfus), x2 (spans three pfus) and x6 (spans seven pfus). the x1, x2, and x6 connections provide fast and efficient connec- tions in the horizontal and vertical directions. the design tools take the output of the synthesis tool a nd places and routes the design. generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the de-sign. clock/control distribution network each machxo2 device has eight clock inputs (pclk [t, c] [banknum]_[2..0]) ? three pins on the left side, two pins each on the bottom and top sides and one pin on the right side. these clock inputs drive the clock nets. these eight inputs can be differential or single-ended and may be used as general purpose i/o if they are not used to drive the clock nets. the machxo2 architecture has three types of clocking resources: edge clocks, primary clocks and secondary high fanout nets. machxo2-1200 and higher density devices have two edge clocks each on the top and bottom edges. edge clocks are used to clock i/o registers and have low injection time and skew. edge clock inputs are from pll outputs, primary clock pads, edge clock bridge outputs and cib sources. spr 16x4 pdpr 16x4 number of slices 3 3 note: spr = single port ram, pdpr = pseudo dual port ram
2-6 architecture lattice semiconductor machxo 2 family data sheet the eight primary clock lines in the primary clock network drive throughout the entire device and can provide clocks for all resources within the device including pfus, ebrs, routing and pics. in addition to the primary clock signals machxo2 devices also have eight secondary high fanout si gnals which can be used for global control signals, such as clock enables, synchronous or asynchronous clears, presets, output enables, etc. internal logic can drive the global clock network for internally-generated global clocks and control signals. the primary clock signals for the machxo2-256 and machxo2-640 are generated from eight 17:1 muxes the available clock sources include eight i/o sources and 9 routing inputs. primary clock signals for the machxo2-1200 and larger devices are generated from eight 27:1 muxes the available clock sources include eight i/o sources, 11 routing inputs, eight clock divider inputs and up to eight sysclock pll outputs. figure 2-5. primary clocks for machxo2 devices 811 clock pads routing primary clock 0 primary clock 1 primary clock 2 primary clock 3 primary clock 4 primary clock 5 primary clock 6 8 edge clock divider primary clocks for machxo2-1200 and larger devices. note: machxo2-640 and smaller devices do not have inputs from edge clock divider. these devices have 17:1 muxes instead of 27:1 muxes. primary clock 7 dynamic clock enable dynamic clock enable dynamic clock enable dynamic clock enable dynamic clock enable 27:1 27:1 27:1 27:1 27:1 27:1 27:1 27:1 27:1 27:1 up to 8 pll outputs dynamic clock enable dynamic clock enable dynamic clock enable clock switch clock switch
2-7 architecture lattice semiconductor machxo 2 family data sheet eight secondary high fanout nets are generated from eight 8:1 muxes as shown in figure 2-6. one of eight inputs to the secondary high fanout net input mux comes from dual function clock pins and remaining seven come from internal routing. figure 2-6. secondary high fanout nets for machxo2 devices sysclock phase loc ked loops (plls) the sysclock plls provide the ability to synthesize cloc k frequencies. the machxo2- 1200 and larger devices have one or more sysclock pll. clki is the reference frequency input to the pll and its source can come from an external i/o pin or from internal routing. clkfb is the feedback signal to the pll which can come from internal routing or an external i/o pin. the feedback divider is used to multiply the reference frequency and thus synthesize a higher frequency clock output. the machxo2 sysclock plls support high resolution (16-bit) frac tional-n synthesis. fr actional-n frequency syn- thesis that allows the user to generate an output clock which is a non-integer multiple of the input frequency. f out = (f in /div in ) * (n.f)/div fbk where: n.f = n + (f/2 16 ) each output has its own output divider, thus allowing the pll to generate different frequencies for each output. the output dividers can have a value from 1 to 128. the clkos2 and clkos3 dividers may also be cascaded together to generate low frequency clocks. the clkop, clkos, clkos2, and clkos3 outputs can all be used to drive the machxo2 clock distribution network directly or general purpose routing resources can be used. 17 8:1 8:1 8:1 8:1 8:1 8:1 8:1 8:1 clock pads routing secondary high fanout net 0 secondary high fanout net 1 secondary high fanout net 2 secondary high fanout net 3 secondary high fanout net 4 secondary high fanout net 5 secondary high fanout net 6 secondary high fanout net 7
2-8 architecture lattice semiconductor machxo 2 family data sheet the lock signal is asserted when the pll determines it has achieved lock and de-asserted if a loss of lock is detected. a block diagram of the pll is shown in figure 2-7. the setup and hold times of the device can be improved by programming a phase shift into the clkos, clkos2, and clkos3 output clocks which will ad vance or delay the output clock with reference to the clkop output clock. this phase shift can be either programmed during configuration or can be adjusted dynamically. in dynamic mode, the pll may lose lock after a phase adjustment on the output used as the feedback source and not relock until the t lock parameter has been satisfied. the machxo2 also has a feature that allows the user to select between two different reference clock sources dynamically. this feature is implem ented using the pllrefcs primitive. the machxo2 pll contains a wishbone port feature that a llows the pll settings, including divider values, to be dynamically changed from the user logic. when using this feature the efb block must also be instantiated in the design to allow access to the wishbone ports. similar to the dynamic phase adjustment, when pll settings are updated through the wishbone port the pll may lose lock and not relock until the t lock parameter has been sat- isfied. for more details on the pll and the wishbone interface, see tn1199, machxo2 sysclock pll design and usage guide . figure 2-7. pll diagram clkop, clkos, clkos2, clkos3 refclk internal feedback fbksel clkop clkos 4 clkos2 clkos3 refclk divider m (1 - 40) lock intlock enclkop, enclkos, enclkos2, enclkos3 rst, resetm, resetc, resetd clkfb clki dynamic phase adjust phasesel[1:0] phasedir phasestep pllwakesync stdby fbkclk divider n (1 - 40) fractional-n synthesizer phase detector, vco, and loop filter . clkos3 divider (1 - 128) clkos2 divider (1 - 128) phase adjust phase adjust phase adjust/ edge trim clkos divider (1 - 128) clkop divider (1 - 128) lock detect clken synch clken synch clken synch clken synch plldato[7:0] , pllack pllclk, pllrst, pllstb, pllwe, plldati[7:0], plladdr[4:0] a0 b0 c0 d0 d1 mux a2 mux b2 mux c2 mux d2 mux dphsrc phase adjust/ edge trim
2-9 architecture lattice semiconductor machxo 2 family data sheet table 2-4 provides signal descriptions of the pll block. sysmem embedded block ram memory the machxo2-640 and larger devices contain sysmem em bedded block rams (ebrs). the ebr consists of a 9- kbit ram, with dedicated input and output registers. this memory can be used for a wide variety of purposes including data buffering, prom for the soft processor and fifo. sysmem memory block the sysmem block can implement single port, dual port, pseudo dual port, or fifo memories. each block can be used in a variety of depths and widths as shown in table 2-5. table 2-4. pll signal descriptions port name i/o description clki i input clock to pll clkfb i feedback clock phasesel[1:0] i select which out put is affected by dynamic phase adjustment ports phasedir i dynamic phase adjustment direction phasestep i dynamic phase step ? toggle sh ifts vco phase adjust by one step. clkop o primary pll output clock (with phase shift adjustment) clkos o secondary pll output clock (with phase shift adjust) clkos2 o secondary pll output clock2 (with phase shift adjust) clkos3 o secondary pll output clock3 (with phase shift adjust) lock o pll lock, asynchronous signal. active high indicates pll is locked to input and feed- back signals. intlock o pll internal lock, asynchronous signal. active high indicates pll lock using internal feedback. dphsrc o dynamic phase source ? ports or wishbone is active stdby i standby signal to power down the pll pllwakesync i pll wake-up sync. enable pll to switch from internal to user feed-back path when the pll wakes up. rst i pll reset without resetting the m-divider. active high reset. resetm i pll reset - includes resetti ng the m-divider. active high reset. resetc i reset for clkos2 output di vider only. active high reset. resetd i reset for clkos3 output di vider only. active high reset. enclkop i enable pll output clkop enclkos i enable pll output clkos when port is active enclkos2 i enable pll output clkos2 when port is active enclkos3 i enable pll output clkos3 when port is active pllclk i pll data bus clock input signal pllrst i pll data bus reset. this resets only the data bus not any register values. pllstb i pll data bus strobe signal pllwe i pll data bus write enable signal plladdr [4:0] i pll data bus address plldati [7:0] i pll data bus data input plldato [7:0] o pll data bus data output pllack o pll data bus acknowledge signal
2-10 architecture lattice semiconductor machxo 2 family data sheet table 2-5. sysmem block configurations bus size matching all of the multi-port memory modes support different widths on each of the ports. the ram bits are mapped lsb word 0 to msb word 0, lsb word 1 to msb word 1, and so on. although the word size and number of words for each port varies, this mapping scheme applies to each port. ram initialization and rom operation if desired, the contents of the ram can be pre-loaded during device configuration. ebr initialization data can be loaded from the ufm. to maximize the number of ufm bits, initialize the ebrs to an all-ze ro pattern. initializing to an all-zero pattern does not use up ufm bits. machxo2 devices have been designed such that multiple ebrs share the same initialization memory space if they are initialized to the same pattern. by preloading the ram block during the chip configuration cycle and disabling the write controls, the sysmem block can also be utilized as a rom. memory cascading larger and deeper blocks of ram can be created using ebr sysmem blocks. typically, the lattice design tools cascade memory transparently, bas ed on specific design inputs. single, dual, pseudo-dual port and fifo modes figure 2-8 shows the five basic memory configurations and their input/output nam es. in all the sysmem ram modes, the input data and addresses for the ports are registered at the input of the memory array. the output data of the memory is optionally registered at the memory array output. memory mode configurations single port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 true dual port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 pseudo dual port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 fifo 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18
2-11 architecture lattice semiconductor machxo 2 family data sheet figure 2-8. sysmem memory primitives table 2-6. ebr signal descriptions port name description active state clk clock rising clock edge ce clock enable active high oce 1 output clock enable active high rst reset active high be 1 byte enable active high we write enable active high ad address bus ? di data in ? do data out ? cs chip select active high aff fifo ram almost full flag ? ff fifo ram full flag ? aef fifo ram almost empty flag ? ef fifo ram empty flag ? rprst fifo ram read pointer reset 1. optional signals. 2. for dual port ebr primitives a trailing ?a? or ?b? in the signal name specifies the ebr port a or port b respectively. 3. for fifo ram mode primitive, a trailing ?r? or ?w? in the si gnal name specifies the fifo read port or write port respec- tively. 4. for fifo ram mode primitive fulli has the same function as csw(2) and emptyi has the same function as csr(2) di[17:0] clkw we fifo ram do[17:0] rst fulli aff ff aef ef clkr re csr[1:0] ore rprst csw[1:0] emptyi rom do[17:0] ad[12:0] clk ce rst cs[2:0] oce ebr ebr ad[12:0] di[8:0] do[8:0] clk ce rst we cs[2:0] oce single-port ram ada[12:0] dia[8:0] clka cea rsta wea csa[2:0] doa[8:0] ocea adb[12:0] b[8:0] clkb ceb rstb web csb[2:0] dob[8:0] oceb true dual port ram adw[8:0] di[17:0] clkw cew rst csw[2:0] adr[12:0] clkr cer do[17:0] csr[2:0] ocer be[1:0] pseudo dual port ram ebr ebr ebr
2-12 architecture lattice semiconductor machxo 2 family data sheet the ebr memory supports three forms of write behavior for single or dual port operation: 1. normal ? data on the output appears only during the read cycle. during a write cycle, the data (at the current address) does not appear on the output. this mode is supported for all data widths. 2. write through ? a copy of the input data appears at the output of the same port. this mode is supported for all data widths. 3. read-before-write ? when new data is being written, the old contents of the address appears at the output. this mode is supported for x1, x2, x4, and x9 data widths. fifo configuration the fifo has a write port with data-in, cew, we and clkw signals. there is a separate read port with data-out, rce, re and clkr signals. the fifo in ternally generates almost full, full, almost empty and empty flags. the full and almost full flags are registered with clkw. the empty and almost empty flags are registered with clkr. table 2-7 shows the range of programming values for these flags. table 2-7. programmable fifo flag ranges the fifo state machine supports two types of reset signals : rsta and rstb. the rsta signal is a global reset that clears the contents of the fifo by resetting the read/write pointer and puts the fifo flags in their initial reset state. the rstb signal is used to reset the read pointer. the purpose of this reset is to retransmit the data that is in the fifo. in these applications it is important to keep careful track of when a packet is written into or read from the fifo. memory core reset the memory core contains data output latches for ports a and b. these are simple latches that can be reset syn- chronously or asynchronously. rsta and rstb are local signals, which reset the output latches associated with port a and port b respectively. the global reset (gsrn) signal resets both ports. the output data latches and associated resets for both ports are as shown in figure 2-9. figure 2-9. memory core reset flag name programming range full (ff) 1 to max (up to 2 n -1) almost full (af) 1 to full-1 almost empty (ae) 1 to full-1 empty (ef) 0 n = address bit width. q set d output data latches memory core port a[18:0] q set d port b[18:0] rstb gsrn programmable disable rsta
2-13 architecture lattice semiconductor machxo 2 family data sheet for further information on the sysmem ebr block, please refer to tn1201, memory usage guide for machxo2 devices . ebr asynchronous reset ebr asynchronous reset or gsr (if used) can only be app lied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the reset is released, as shown in figure 2-10. the gsr input to the ebr is always asynchronous. figure 2-10. ebr asynchronous reset (including gsr) timing diagram if all clock enables remain enabled, the ebr asynchronous reset or gsr may only be applied and released after the ebr read and write clock inputs are in a steady state condition for a minimum of 1/f max (ebr clock). the reset release must adhere to the ebr synchronous reset setup time before the next active read or write clock edge. if an ebr is pre-loaded during configuration, the gsr input must be disabled or the release of the gsr during device wake up must occur before the release of the device i/os becoming active. these instructions apply to all ebr ram, rom and fifo implementations. for the ebr fifo mode, the gsr sig- nal is always enabled and the we and re signals act like the clock enable signals in figure 2-10. the reset timing rules apply to the rpreset input versus the re input an d the rst input versus the we and re inputs. both rst and rpreset are always asynchronous ebr inputs. for more details refer to tn1201, memory usage guide for machxo2 devices . note that there are no reset restrictions if the ebr syn chronous reset is used and the ebr gsr input is disabled. programmable i/o cells (pic) the programmable logic associated with an i/o is called a pio. the individual pio are connected to their respec- tive sysio buffers and pads. on the machxo2 devices, the pio cells are assembled into groups of four pio cells called a programmable i/o cell or pic. the pics are placed on all four sides of the device. on all the machxo2 devices, two adjacent pios can be combined to provide a complementary output driver pair. the i/o pin pairs are labeled as ?t? and ?c? to distinguish between the true and complement pins. the machxo2-1200 and higher density devices contain enhanced i/o capability. all pio pairs on these larger devices can implement differential receivers. half of the pio pairs on the top edge of these devices can be config- ured as true lvds transmit pairs. the pio pairs on the bottom edge of these higher density devices have on-chip differential termination and also provide pci support. reset clock clock enable
2-14 architecture lattice semiconductor machxo 2 family data sheet figure 2-11. group of four programmable i/o cells 1 pic pio a output register block & tristate register block pin a input register block pio b output register block & tristate register block pin a input register block pio c output register block & tristate register block pin a input register block notes: 1. input gearbox is available only in pic on the bottom edge of machxo2-1200 and larger devices. 2. output gearbox is available only in pic on the top edge of machxo2-1200 and larger devices. pio d output register block & tristate register block pin a input register block core logic/ routing input gearbox output gearbox
2-15 architecture lattice semiconductor machxo 2 family data sheet pio the pio contains three blocks: an input register block, output register block and tri-state register block. these blocks contain registers for operating in a variety of modes along with the necessary clock and selection logic. table 2-8. pio signal list input register block the input register blocks for the pios on all edges, contain delay elements and regis-ters that can be used to con- dition high-speed interface signals, such as ddr generic is part of the source synchronous interfaces, before they are passed to the device core. in addition to this functionality, the input register blocks for the pios on the right edge include built-in logic to interface to ddr memory. figure 2-12 shows the input register block for the pios located on the left, top and bottom edges. figure 2-13 shows the input register block for the pios on the right edge. left, top, bottom edges input signals are fed from the sysio buffer to the input register block (as signal d). if desired, the input signal can bypass the register and delay elements and be used directly as a combinatorial signal (indd), and a clock (inck). if an input delay is desired, users can select a fixed del ay. i/os on the bottom edge also have a dynamic delay, del[4:0]. the delay, if selected, reduces input register hold time requirements when using a global clock. the input block allows two modes of operation. in single data rate (sdr) the data is registered with the system clock (sclk) by one of the registers in the single data rate sync register block. in generic ddr mode, two registers are used to sample the data on the positive and negative edges of the system clock (sclk) signal, creating two data streams. pin name i/o type description ce input clock enable d input pin input from sysio buffer. indd output register bypassed input. inck output clock input q0 output ddr positive edge input q1 output registered input/ddr negative edge input d0 input output signal from the core (sdr and ddr) d1 input output signal from the core (ddr) td input tri-state signal from the core q output data output signals to sysio buffer tq output tri-state output signals to sysio buffer dqsr90 1 input dqs shift 90-degree read clock dqsw90 1 input dqs shift 90-degree write clock ddrclkpol 1 input ddr input register polar ity control signal from dqs sclk input system clock for input and output/tri-state blocks. rst input local set reset signal 1. available in pio on right edge only.
2-16 architecture lattice semiconductor machxo 2 family data sheet figure 2-12. machxo2 input register block di agram (pio on left, top and bottom edges) right edge the input register block on the right edge is a superset of the same block on the top, bottom, and left edges. in addition to the modes described above, the input register block on the right edge also supports ddr memory mode. in ddr memory mode, two registers are used to sample the data on the positive and negative edges of the modi- fied dqs (dqsr90) in the ddr memory mode creating two data streams. before entering the core, these two data streams are synchronized to the system clock to generate two data streams. the signal ddrclkpol controls the pola rity of the clock used in the synchr onization registers. it ensures ade- quate timing when data is transfer red to the system clock domain from the dqs do main. the dqsr90 and ddrclkpol signals are generated in the dqs read-write block. figure 2-13. machxo2 input register block diagram (pio on right edge) output register block the output register block registers signals from the core of the device before they are passed to the sysio buffers. left, top, bottom edges in sdr mode, d0 feeds one of the flip-flops that then feeds the output. the flip-flop can be configured as a d-type register or latch. sclk inck q1 q0 indd d q0 q1 d q programmable delay cell d/l q d q d q q1 q0 indd d dqsr90 q0 q1 sclk s0 s1 ddrclkpol programmable delay cell d/l q inck d q d q d q d q d q d q d q
2-17 architecture lattice semiconductor machxo 2 family data sheet in ddr generic mode, d0 and d1 inputs ar e fed into registers on the positive edge of the clock. at the next falling edge the registered d1 input is registered into the register q1. a multiplexer running off the same clock is used to switch the mux between the outp uts of registers q0 and q1 that will then fe ed the output. figure 2-14 shows the output register block on the left, top and bottom edges. figure 2-14. machxo2 output register block diagram (pio on the left, top and bottom edges) right edge the output register block on the right edge is a superset of the output register on left, top and bottom edges of the device. in addition to supporting sdr and generic ddr modes, the output register blocks for pios on the right edge include additional logic to support ddr-memory interfaces. operation of this block is similar to that of the out- put register block on other edges. in ddr memory mode, d0 and d1 inputs are fed into registers on the positive edge of the clock. at the next falling edge the registered d1 input is registered into the register q1. a multiplexer running off the dqsw90 signal is used to switch the mux between the out puts of registers q0 and q1 that will then feed the output. figure 2-15 shows the output register block on the right edge. output path tq d/l q td tri-state path q d1 d q d q q1 d/l q q0 d0 sclk
2-18 architecture lattice semiconductor machxo 2 family data sheet figure 2-15. machxo2 output register block diagram (pio on the right edges) tri-state register block the tri-state register block registers tri-state control signals from the core of the device before they are passed to the sysio buffers. the block contains a register for sdr operation. in sdr, td input feeds one of the flip-flops that then feeds the output. the tri-state register blocks on the right edge contain an additional register for ddr memory operation. in ddr memory mode, the register ts input is fed into another register that is clocked using the dqsw90 signal. the out- put of this register is used as a tri-state control. input gearbox each pic on the bottom edge has a built-in 1:8 input gearbox. each of these input gearboxes may be programmed as a 1:7 de-serializer or as one iddrx4 (1:8 gearbox) gearbox or as two iddrx2 (1:4) gearboxes. table 2-9 shows the gearbox signals. table 2-9. input gearbox signal list name i/o type description d input high-speed data input after programmable delay in pio a input register block alignwd input data alignment signal from device core sclk input slow-speed system clock eclk[1:0] input high-speed edge clock rst input reset q[7:0] output low-speed data to device core: video rx(1:7): q[6:0] gddrx4(1:8): q[7:0] gddrx2(1:4)(iol-a): q4, q5, q6, q7 gddrx2(1:4)(iol-c): q0, q1, q2, q3 d q d1 d q q1 d/l q q0 d0 dqsw90 q sclk d q tq d/l q t0 td output register block tristate register block
2-19 architecture lattice semiconductor machxo 2 family data sheet these gearboxes have three stage pipeline registers. the first stage registers sample the high-speed input data by the high-speed edge clock on its rising and falling edges. the second stage registers perform data alignment based on the control signals update and sel from the control block. the third stage pipeline registers pass the data to the device core synchronized to the low-speed system clock. figure 2-16 shows a block diagram of the input gearbox. figure 2-16. input gearbox d q d eclk0/1 sclk q21 q0_ s2 s0 d q d q t2 t0 q0 q2 d q d q ce d q ce d q q65 q43 s6 s4 d q d q t6 t4 d q cdn d q ce d q cdn ce d q q54 q_6 s3 s5 d d t3 t5 q6 d q d q ce d q ce d q q10 q32 s1 d t1 d q d q ce q65 q65 q43 q43 q21 q10 q21 q32 q54 q_6 q54 q32 sel0 q4 q5 q1 q3 s7 d q t7 d q ce q7 update q_6
2-20 architecture lattice semiconductor machxo 2 family data sheet more information on the input gearbox is available in tn1203, implementing high-speed interfaces with machxo2 devices . output gearbox each pic on the top edge has a built-in 8:1 output gearbox. each of these output gearboxes may be programmed as a 7:1 serializer or as one oddrx4 (8:1 gearbox) gearbox or as two oddrx2 (4:1) gearboxes. table 2-10 shows the gearbox signals. table 2-10. output gearbox signal list the gearboxes have three stage pipeline registers. the first stage registers sample the low-speed input data on the low-speed system clock. the second stage registers transfer data from the low-speed clock registers to the high- speed clock registers. the third stage pipeline registers controlled by high-speed edge clock shift and mux the high-speed data out to the sysio buffer. figure 2-17 shows the output gearbox block diagram. name i/o type description q output high-speed data output d[7:0] input low-speed data from device core video tx(7:1): d[6:0] gddrx4(8:1): d[7:0] gddrx2(4:1)(iol-a): d[3:0] gddrx2(4:1)(iol-c): d[7:4] sclk input slow-speed system clock eclk [1:0] input high-speed edge clock rst input reset
2-21 architecture lattice semiconductor machxo 2 family data sheet figure 2-17. output gearbox more information on the output gearbox is available in tn1203, implementing high-speed interfaces with machxo2 devices . ddr memory support certain pics on the right edge of machxo2-1200 and larger devices, have additional circuitry to allow the imple- mentation of ddr memory interfaces. there are two groups of 14 or 12 pios each on the right edge with additional circuitry to implement ddr memory inte rfaces. this capability allows the implem entation of up to 16-bit wide mem- ory interfaces. one pio from each grou p contains a control element, the dqs read/write block, to facilitate the d4 d0 d3 d1 s1 t1 s0 qc oddrx2_a oddrx2_c oddrx2_c eclk0/1 q45 q67 s4 s6 d q d q t4 t6 d6 d q d q ce d q ce 0 1 0 1 q01 q23 s0 s2 t0 t2 q32 q10 s5 s3 d q t5 t3 ce 0 1 d q q76 q54 s7 d q t7 d q d q d q ce 0 1 s2 s4 gnd s7 s6 s5 s3 d2 d7 d5 sclk 0 1 0 1 0 1 1 0 1 q34 q56 q67 gnd q45 s1 q12 sel /0 update q23 q/qa d q d q d q d q d q d q d q d q d q d q d q 0 1 0 1 0 1 0 1 0 1 0 ce ce d q ce d q ce 0 1 0 1 cdn
2-22 architecture lattice semiconductor machxo 2 family data sheet generation of clock and control si gnals (dqsr90, dqsw90, ddrclkpol a nd datavalid). these clock and con- trol signals are distributed to the other pio in the group through dedicated low skew routing. dqs read write block source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at the input register. for most interfaces a pll is used for this adjustment. however, in ddr memories the clock (referred to as dqs) is not free-running so this approac h cannot be used. the dqs read write block provides the required clock alignment for ddr memory interfaces. dqsr90 and dqsw90 signals are generated by the dqs read write block from the dqs input. in a typical ddr memory interface design, the phase relationship between the incoming delayed dqs strobe and the internal system clock (during the read cycle) is unkn own. the machxo2 family contains dedicated circuits to transfer data between these domains. to prevent set-up and hold violations, at the domain transfer between dqs (delayed) and the system clock, a clock polarity selector is used. this circuit changes the edge on which the data is registered in the synchronizing registers in the input regist er block. this requires evaluation at the start of each read cycle for the correct clock polarity. prior to the read operation in ddr memories, dqs is in tri-state (pulled by termination). the ddr memory device drives dqs low at the start of the preamble state. a dedicated circuit in the dqs read write block detects the first dqs rising edge after the preamble state and generates the ddrclkpol signal. this signal is used to control the polar ity of the clock to the synchronizing registers. the temperature, voltage and process variations of the dqs delay block are compensated by a set of calibration signals (6-bit bus) from a dll on the right edge of the device. the dll loop is compensated for temperature, volt- age and process variations by the system clock and feedback loop. sysio buffer each i/o is associated with a flexible buffer referred to as a sysio buffer. these buffers are arranged around the periphery of the device in groups referred to as banks. the sysio buffers allow users to implement a wide variety of standards that are found in today?s systems including lvcmos, ttl, pci, sstl, hstl, lvds, blvds, mlvds and lvpecl. each bank is capable of supporting multiple i/o standards. in the machxo2 devices, single-ended output buffers, ratioed input buffers (lvttl, lvcmos and pci), differential (lvds) and referenced input buffers (sstl and hstl) are powered using i/o supply voltage (v ccio ). each sysio bank has its own v ccio . in addition, each bank has a voltage reference, v ref , which allows the use of referenced input buffers independent of the bank v ccio . machxo2-256 and machxo2-640 devices contain single-ended ratioed input buffers and single-ended output buf- fers with complementary outputs on all the i/o banks. note that the single-ended input buffers on these devices do not contain pci clamps. in addition to the single-ended i/o buffers these two devices also have differential and ref- erenced input buffers on all i/os. the i/os are arranged in pairs, the two pads in the pair are de-scribed as ?true? and ?comp?, where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. machxo2-1200, machxo2-2000, machxo2-4000 and machxo2-7000 devices contain three types of sysio buffer pairs. 1. left and right sysio buffer pairs ? the sysio buffer pairs in the left and right banks of the device consist of two single-ended output drivers and two single-ended input buffers (for ratioed inputs such as lvcmos and lvttl). the i/o pairs on the left and right of the devices also have differential and referenced input buffers. 2. bottom sysio buffer pairs ? the sysio buffer pairs in the bottom bank of the device consist of two single-ended output drivers and two sin- gle-ended input buffers (for ratioed inputs such as lvcmos and lvttl). the i/o pairs on the bottom also have differential and referenced input buffers. only the i/os on the bottom banks have programmable pci clamps
2-23 architecture lattice semiconductor machxo 2 family data sheet and differential input termination. the pci clamp is enabled after v cc and v ccio are at valid operating levels and the device has been configured. 3. top sysio buffer pairs ? the sysio buffer pairs in the top bank of the device co nsist of two single-ended output drivers and two single- ended input buffers (for ratioed inputs such as lvcmos and lvttl). the i/o pairs on the top also have differ- ential and referenced i/o buffers. half of the sysio buffer pairs on the top edge have true differential outputs. the sysio buffer pair comprising of the a and b pios in every pic on the top edge have a differential output driver. the referenced input buffer can also be configured as a differential input buffer. typical i/o behavior during power-up the internal power-on-reset (por) signal is deactivated when v cc has reached v porup level defined in the power-on-reset voltage table in the dc and switching characteristics sectio n of this data sheet. after the por signal is deactivated, the fpga core logic becomes active. it is the us er?s responsibility to ensure that all v ccio banks are active with valid input logic levels to properly control the output logic states of all the i/o banks that are critical to the application. the default configuration of the i/o pins in a blank device is tri-state with a weak pull- down to gnd. the i/o pins will mainta in the blank configuration until v cc and v ccio (for i/o banks containing con- figuration i/os) have reached v porup levels at which time the i/os will ta ke on the user-configured settings. there are various ways a user can ensure that there are no spurious signals on critical outputs as the device pow- ers up. these are discussed in more detail in tn1202, machxo2 sysio usage guide . supported standards the machxo2 sysio buffer supports both single-ended and differential standards. single-ended standards can be further subdivided into lvcmos, lvttl, and pci. the buffer supports the lvttl, pci, lvcmos 1.2, 1.5, 1.8, 2.5, and 3.3v standards. in the lvcmos and lvttl modes, the buffer has individually configurable options for drive strength, bus maintenance (weak pull-up, weak pull-down, bus-keeper latch or none) and open drain. blvds, mlvds and lvpecl output emulation is supported on all devices. the machxo2-1200 and higher devices sup- port on-chip lvds output buffers on approximately 50% of the i/os on the top bank. differential receivers for lvds, blvds, mlvds and lvpecl are supported on all banks of machxo2 devices. pci support is provided in the bot- tom bank of the machxo2-1200 and higher density devices. table 2-11 summarizes the i/o characteristics of the machxo2 plds. tables 2-11 and 2-12 show the i/o standards (together with their supply and reference voltages) supported by the machxo2 devices. for further information on utilizing the sysi o buffer to support a variet y of standards please see tn1202, machxo2 sysio usage guide . table 2-11. i/o support device by device machxo2-256, machxo2-640 machxo2-1200 machxo2-2000, machxo2-4000, machxo2-7000 number of i/o banks 4 4 6 type of input buffers single-ended (all i/o banks) differential receivers (all i/o banks) single-ended (all i/o banks) differential receivers (all i/o banks) differential input termination (bottom side) single-ended (all i/o banks) differential receivers (all i/o banks) differential input termination (bottom side) types of output buffers single-ended buffers with complementary outputs (all i/o banks) single-ended buffers with complementary outputs (all i/o banks) differential buffers with true lvds outputs (50% on top side) single-ended buffers with complementary outputs (all i/o banks) differential buffers with true lvds outputs (50% on top side)
2-24 architecture lattice semiconductor machxo 2 family data sheet table 2-12. supported input standards differential output emulation capability all i/o banks all i/o banks all i/o banks pci clamp support no clamp on bottom side only clamp on bottom side only vccio (typ.) input standard 3.3v 2.5v 1.8v 1.5 1.2v single-ended interfaces lv t t l ?? 2 ? 2 ? 2 lv c m o s 3 3 ?? 2 ? 2 ? 2 lv c m o s 2 5 ? 2 ?? 2 ? 2 lv c m o s 1 8 ? 2 ? 2 ?? 2 lv c m o s 1 5 ? 2 ? 2 ? 2 ?? 2 lv c m o s 1 2 ? 2 ? 2 ? 2 ? 2 ? pci 1 ? sstl18 (class i, class ii) ? sstl25 (class i, class ii) ? hstl18 (class i, class ii) ? differential interfaces lv d s ?? blvds, mvds, lvpecl, rsds ???? 1. bottom banks of machxo2-1200 and higher density devices only. 2. reduced functionality. refer to tn1202, machxo2 sysio usage guide for more detail. machxo2-256, machxo2-640 machxo2-1200 machxo2-2000, machxo2-4000, machxo2-7000 number of i/o banks 4 4 6
2-25 architecture lattice semiconductor machxo 2 family data sheet table 2-13. supported output standards sysio buffer banks the numbers of banks vary between the devices of this family. six banks surround the three larger devices, the machxo2-2000, machxo2-4000 and machxo2-7000 (one bank on the top, right and bottom side and three banks on the left side). the machxo2-256, machxo2-640 and machxo2-1200 have four banks (one bank per side). fig- ures 2-18 and 2-19 show the sysio banks and their associated supplies for all devices. output standard v ccio (typ.) single-ended interfaces lv t t l 3 . 3 lvcmos33 3.3 lvcmos25 2.5 lvcmos18 1.8 lvcmos15 1.5 lvcmos12 1.2 lvcmos33, open drain ? lvcmos25, open drain ? lvcmos18, open drain ? lvcmos15, open drain ? lvcmos12, open drain ? pci33 3.3 sstl25 (class i) 2.5 sstl18 (class i) 1.8 hstl18(class i) 1.8 differential interfaces lv d s 1, 2 2.5 blvds, mlvds, rsds 2 2.5 lvpecl 2 3.3 1. machxo2-1200 and larger devices have dedicated lvds buffers. 2. these interfaces can be emulated with external resistors in all devices.
2-26 architecture lattice semiconductor machxo 2 family data sheet figure 2-18. machxo2-2000, machxo2-4000 and machxo2-7000 banks figure 2-19. machxo2-256, machxo2-640 and machxo2-1200 banks bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 vccio0 vccio2 gnd gnd vccio1 gnd gnd gnd gnd vccio5 vccio4 vccio3 bank 0 bank 1 bank 2 bank 3 vccio0 vccio2 gnd gnd vccio1 gnd vccio3 gnd
2-27 architecture lattice semiconductor machxo 2 family data sheet hot socketing the machxo2 devices have been carefully designed to ensure predictable behavior during power-up and power- down. leakage into i/o pins is controlle d to within specified limits. this allows for easy integration with the rest of the system. these cap abilities make the machxo2 ideal for many mu ltiple power supply and hot-swap applica- tions. on-chip oscillator every machxo2 device has an internal cm os oscillator. the oscilla tor output can be routed as a clock to the clock tree or as a reference clock to the sysclock pll using general routing resources. t he oscillator freq uency can be divided by internal logic. th ere is a dedicated programming bit and a user input to enable/disable the oscillator. the oscillator frequency ranges fr om 2.08 mhz to 133 mhz. the software def ault value of the master clock (mclk) is nominally 2.08 mhz. when a different mclk is selected during the design process, the following sequence takes place: 1. device powers up with a nominal mclk frequency of 2.08 mhz. 2. during configuration, users select a different master clock frequency. 3. the mclk frequency changes to the selected frequency once the clock configuration bits are received. 4. if the user does not select a master clock frequency, th en the configuration bitstream defaults to the mclk fre- quency of 2.08 mhz. table 2-14 lists all the available mclk frequencies. table 2-14. available mclk frequencies embedded hardened ip func tions and user flash memory all machxo2 devices provide embedded hardened functions such as spi, i 2 c and timer/counter. machxo2-640 and higher density devices also provide user flash memory (ufm). these embedded blocks interface through the wishbone interface with routing as shown in figure 2-20. mclk (mhz, nominal) mclk (mhz, nominal) mclk (mhz, nominal) 2.08 (default) 9.17 33.25 2.46 10.23 38 3.17 13.3 44.33 4.29 14.78 53.2 5.54 20.46 66.5 7 26.6 88.67 8.31 29.56 133
2-28 architecture lattice semiconductor machxo 2 family data sheet figure 2-20. embedded function block interface hardened i 2 c ip core every machxo2 device contains two i 2 c ip cores. these are the primary and secondary i 2 c ip cores. either of the two cores can be configured either as an i 2 c master or as an i 2 c slave. the only difference between the two ip cores is that the primary core has pre-assigned i/o pins whereas users can assign i/o pins for the secondary core. when the ip core is configured as a master it will be able to control other devices on the i 2 c bus through the inter- face. when the core is configured as the slave, the device will be able to prov ide i/o expansion to an i 2 c master. the i 2 c cores support the following functionality: ? configurable master/slave mode ? 7-bit and 10-bit addressing ? multi-master arbitration support ? clock stretching ? up to 400khz data transfer speed ? general call support ? interface to custom logic through 8-bit wishbone interface embedded function block (efb) core logic/ routing efb wishbone interface i 2 c (primary) i 2 c (secondary) spi timer/counter pll0 pll1 configuration logic ufm i/os for i 2 c (primary) i/os for spi i/os for i 2 c (secondary) indicates connection through core logic/routing. power control
2-29 architecture lattice semiconductor machxo 2 family data sheet figure 2-21. i 2 c core block diagram table 2-15 describes the signals interfacing with the i 2 c cores. table 2-15. i 2 c core signal description hardened spi ip core every machxo2 device has a hard spi ip core that can be configured as a spi master or slave. when the ip core is configured as a master it will be able to control other spi enab led chips connected to the spi bus. when the core is configured as the slave, the device will be able to in terface to an external spi master. the spi ip core on machxo2 devices supports the following functions: ? configurable master and slave modes ? dull-duplex data transfer ? mode fault error flag with cpu interrupt capability ? double-buffered data register ? serial clock with programmable polarity and phase ? lsb first or msb first data transfer ? interface to custom logic through 8-bit wishbone interface signal name i/o description scli i i 2 c clock line input, can be used for both slave mode and master mode sclo o i 2 c clock line output, can only be used for master mode scloen o i 2 c clock line output enable, active low. can only be used for master mode sdai i i 2 c data line input, for both slave and master modes sdao o i 2 c data line output, for both slave and master modes sdaoen o i 2 c data line output enable, active low. for both slave and master modes irqo o interrupt signal for processor. the signal will be sent to the host through sci. efb scl sda configuration logic core logic/ routing power control i 2 c registers efb wishbone interface control logic i 2 c function
2-30 architecture lattice semiconductor machxo 2 family data sheet figure 2-22. spi core block diagram table 2-16 describes the signals interfacing with the i 2 c cores. table 2-16. spi core signal description hardened timer/counter machxo2 devices provide a hard timer/counter ip core. this timer/counter is a general purpose, bi-directional, 16-bit timer/counter module with independent output compare units and pwm support. the timer/counter sup- ports the following functions: ? supports following modes of operation: ? watchdog timer ? clear timer on compare match ?fast pwm ? phase and frequency correct pwm ? programmable clock input source ? programmable input clock prescaler ? one static interrupt output to routing ? one wake-up interrupt to on-chip standby mode controller. ? three independent interrupt sources: overflow, output compare match, and input capture signal name i/o m/s description spi_csn[0] o m spi master chip-select output spi_csn[1..7] o m additional spi chip-select outputs (total up to eight slaves) spi_scsn i s spi slave chip-select input spi_irq o m/s interrupt request spi_clk i/o m/s spi clock. output in master mode. input in slave mode. spi_miso i/o m/s spi data. input in ma ster mode. output in slave mode. spi_mosi i/o m/s spi data. output in master mode. input in slave mode. efb spi function core logic/ routing efb wishbone interface spi registers control logic configuration logic miso mosi sck mcsn scsn
2-31 architecture lattice semiconductor machxo 2 family data sheet ? auto reload ? time-stamping support on the input capture unit ? waveform generation on the output ? glitch-free pwm waveform generation with variable pwm period ? internal wishbone bus access to the control and status registers ? stand-alone mode with preloaded control registers and direct reset input figure 2-23. timer/c ounter block diagram table 2-17. timer/count er signal description for more details on these embedded functions, please refer to tn1203, implementing high-speed interfaces with machxo2 devices . user flash memory (ufm) machxo2-640 and higher density devices provide a user flash memory block, which can be used for a variety of applications including storing a portion of the configuration image, initializing ebrs, to store prom data or, as a general purpose user flash memory. the ufm block connects to the device core through the embedded function block wishbone interface. users can also access the ufm block through the jtag, i 2 c and spi interfaces of the device. the ufm block offers the following features: ? non-volatile storage up to 256kbits ? 100k write cycles ? byte addressable for read access. write access is performed in 128-byte pages. ? program, erase, and busy signals ? auto-increment addressing ? wishbone interface port i/o description tcclki i timer/counter input clock signal tcrstn i register tc_rstn_ena is preloaded by configuration to always keep this pin enabled tcic i input capture trigger event, applicable for non-pwm modes with wishbone interface. if enabled, a rising edge of this signal will be detected and synchronized to capture tc_cnt value into tc_icr for time-stamping. tcint o without wishbone ? can be used as overflow flag with wishbone ? controlled by three irq registers tcoc o timer counter output signal efb timer/counter core logic routing pwm efb wishbone interface timer/ counter registers control logic
2-32 architecture lattice semiconductor machxo 2 family data sheet for more information on the ufm, please refer to tn1205, using user flash memory an d hardened control func- tions in machxo2 devices . standby mode and power saving options machxo2 devices are availabl e in three options for maximum flexibility: ze, hc and he devices. the ze devices have ultra low static and dynamic power consumption. these devices use a 1.2v core voltage that further reduces power consumption. the hc and he devices are designed to provide high performance. the hc devices have a built-in voltage regulator to allow for 2.5v v cc and 3.3v v cc while the he devices operate at 1.2v v cc . machxo2 devices have been designed with features that allow users to meet the static and dynamic power requirements of their applications by controlling various device subsystems such as the bandgap, powe r-on-reset circuitry, i/o bank controllers, power guard, on-chip oscillator, plls, etc. in order to maximize power savings machxo2 devices support an ultra low power stand-by mode. while most of these features are available in all three device types, these features are mainly intend ed for use with machxo2 ze devices to manage power con- sumption. in the stand-by mode the machxo2 devices are powered on and configured. internal logic, i/os and memories are switched on and remain operational, as the user logic waits for an external input. the device enters this mode when the standby input of the standby controller is toggled or when an appropriate i 2 c or jtag instruction is issued by an external master. various subsystems in the device such as the band gap, power-on-reset circuitry etc can be configured such that they are automatically turned ?off? or go into a low power consumption state to save power when the device enters this state. table 2-18. machxo2 power saving features description for more details on the standby mode refer to tn1198, power estimation and management for machxo2 devices . power on reset machxo2 devices have power-on reset circuitry to monitor v ccint and v ccio voltage levels during power-up and operation. at power-up, the por circuitry monitors v ccint and v ccio (for the main configuration i/o bank 0) volt- device subsystem feature description bandgap the bandgap can be turned off in standby mode. when the bandgap is turned off ana- log circuitry such as the por, plls, on-chi p oscillator, and, referenced and differential ? i/o buffers are also turned off. bandgap can only be turned off for 1.2v devices. power-on-reset (por) the por can be turned off in standby mode. th is monitors vcc levels. in the event of unsafe v cc drops, this circuit reconfigures the device. when the por circuitry is turned off limited power detector circuitry is still active. this option is only recommended for ap- plications in which the power supply rails are reliable. on-chip oscillator the on-chip oscillator has two power saving feat ures. it may be switched off if it is not needed in your design. it can also be turned off in standby mode. pll similar to the on-chip oscillator the pll also has two power saving features. it can be statically switched off if it is not needed in a design. it can also be turned off in standby mode. the pll will wait until all output cloc ks from the pll are driven low before power- ing off. i/o bank controller referenced and differential i/o buffers (use d to implement standards such as hstl, sstl and lvds) consume more than ratioed single-ended i/os such as lvcmos and lvttl. the i/o bank controller allows the user to turn these i/os off dynamically on a per bank selection. dynamic clock enable for primary clock nets each primary clock net can be dynamically disabled to save power. power guard power guard is a feature implemented in input buffers. this feature allows users to switch off the input buffer when it is not n eeded. this feature can be used in both clock and data paths. its biggest impact is that in t he standby mode it can be used to switch off clock inputs that are distributed using general routing resources.
2-33 architecture lattice semiconductor machxo 2 family data sheet age levels and triggers download from the on-chi p configuration flash memory after reaching the v porup level specified in the power-on-reset voltage table in the dc and switching characteristics section of this data sheet. for devices without voltage regulators (ze and he devices), v ccint is the same as the v cc supply voltage. for devices with voltage regu lators (hc devices), v ccint is regulated from the v cc supply voltage. from this voltage reference, the time taken for configuration and entry in to user mode is specified as flash download time (t re- fresh ) in the dc and switching characteristics section of this data sheet. before and during configuration, the i/os are held in tri-state. i/os are released to user functionality once the device has finished configuration. note that for hc devices, a separate por circuit monitors external v cc voltage in addition to the por circuit that monitors the internal post-regulated power supply voltage level. once the device enters into user mode the por circuitry can optionally continue to monitor v ccint levels. if v ccint drops below v pordnbg level (with the bandgap circuitry switched on) or below v pordnsram level (with the band- gap circuitry switched off to conserve power) device func tionality cannot be guaranteed. in such a situation the por issues a reset and begins monitoring the v ccint and v ccio voltage levels. v pordnbg and v pordnsram are both specified in the power-on-reset vo ltage table in the dc and switching characteristics section of this data sheet. note that once a ze or he device enters user mode, users can switch off the bandgap to conserve power. when the bandgap circuitry is switched off, the por circuitry also shuts down. the device is designed such that a mini- mal, low power por circuit is still ope rational (this corresponds to the v pordnsram reset point described in the paragraph above). however this circuit is not as accurate as the one that operates when the bandgap is switched on. the low power por circuit emulates an sram cell and is biased to trip before the vast majority of sram cells flip. if users are concerned about the v cc supply dropping below v cc (min) they should not shut down the bandgap circuit. configuration and testing this section describes the configuration and testing features of the machxo2 family. ieee 1149.1-compliant b oundary scan testability all machxo2 devices have boundary sc an cells that are accessed through an ieee 1149.1 comp liant test access port (tap). this allows functional testing of the circuit boa rd, on which the device is mounted, through a serial scan path that can access all critical logic nodes. internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. the test access port consists of dedicated i/os: tdi, tdo, tck and tms. the test access port shares its power supply with v ccio bank 0 and can operate with lvcmos3.3, 2.5, 1.8, 1.5, and 1.2 standards. for more details on boundary scan test, please see information regarding additional technical documentation at the end of this data sheet. device configuration all machxo2 devices contain two ports that can be used for device configuration. the test access port (tap), which supports bit-wide configuration and the sysconfig port which supports serial, dual-bit, quad-bit or byte- wide configuration. the tap supports both the ieee stan dard 1149.1 bo undary scan specification and the ieee standard 1532 in-system configuration specification. there are various ways to configure a machxo2 device: 1. internal flash download 2. jtag 3. standard serial peripheral interface (spi and spim modes) ? interface to boot prom memory 4. system microprocessor to drive a serial slave spi port (sspi mode) 5. standard i 2 c interface to system microproce ssor or to boot prom memory 6. slave serial configuration (serial configuration mode)
2-34 architecture lattice semiconductor machxo 2 family data sheet upon power-up, the configuration sram is ready to be configured using the selected sysconfig port. once a con-figuration port is selected, it will remain active throughout that configuration cycle. the ieee 1149.1 port can be activated any time after power-up by sending the appropriate command through the tap port. optionally the de- vice can run a crc check upon entering the user mode. th is will ensure that the devi ce was configured correctly. the sysconfig port has 10 dual-function pins which can be used as general purpose i/os if they are required for configuration. see tn1204, machxo2 programming and configuration usage guide for more information about using the dual-use pins as general purpose i/os. lattice design software uses proprietary compression te chnology to compress bit-streams for use in machxo2 devices. use of this technology allows lattice to provide a lower cost solution. in the unlikely event that this technol- ogy is unable to compress bitstreams to fit into the amount of on-chip flash memory there are a variety of tech- niques that can be utilized to allow th e bitstream to fit in th e on-chip flash memory. fo r more details, refer to tn1204, machxo2 programming and configuration usage guide . the test access port (tap) has five dual purpose pins (tdi, tdo, tms, tck and jtagenb). these pins are dual function pins - tdi, tdo, tms and tck can be used as general purpose i/o if desired. for more details, refer to tn1204, machxo2 programming and configuration usage guide . transfr (transparent field reconfiguration) transfr is a unique lattice technology that allows users to update their logic in the field without interrupting sys- tem operation using a single command. for more details refer to tn1087, minimizing system interruption during configuration using transfr technology for details. security and one-time programmable mode (otp) for applications where security is important, the lack of an external bitstream provides a solution that is inherently more secure than sram-based fpgas. this is further enhanced by device locking. machxo2 devices contain security bits that, when set, prevent the readback of the sram configuration and non-volatile flash memory spaces. the device can be in one of two modes: 1. unlocked ? readback of the sram configuration and non-volatile flash memory spaces is allowed. 2. permanently locked ? the device is permanently locked. once set, the only way to clear the security bits is to erase the device. to further complement the security of the device, a one time programmable (otp) mode is available. on ce the device is set in this mode it is not possible to erase or re-program the flash portion of the device. for more details, refer to tn1204, machxo2 programming and configuration usage guide . dual boot machxo2 devices can optionally boot from two patterns, a primary bitstream and a golden bitstream. if the primary bitstream is found to be corrupt while being downloaded into the sram (the done pin stays low), the device shall then automatically re-boot from the golden bitstream. note that the either the primary bitstream or golden bitstream can reside in the on-chip flash. the other image has to reside in an external spi flash. if no golden bitstream is included, machxo2 devices will attempt to read the primary bitstream twice be fore flagging an error. for more details, refer to tn1204, machxo2 programming and configuration usage guide . soft error detect (sed) the sed is a crc check of the sram cells after the device is configured. this check ensures that the sram cells were configured successfully. this feature is enabled by a configuration bit option. the sed can also be initiated in user mode via an input to the fabric. the clock for the sed circuit is generated using a dedicated divider. the undi- vided clock from the on-chip oscillator is input to this divider. for low powe r applications users can switch off the sed circuit. for more details, refer to tn1204, machxo2 programming and configuration usage guide .
2-35 architecture lattice semiconductor machxo 2 family data sheet traceid each machxo2 device contains a unique (per device), traceid that can be used for tracking pur-poses or for ip security applications. the traceid is 64 bits long. 8 out 64 bits are user-programmable, the remaining 56 bits are factory-programmed. the traceid is accessible through the efb wishbone interface and can also be accessed through the spi, i 2 c, or, jtag interfaces. density shifting the machxo2 family has been designed to enable density migration within the same package. furthermore, the architecture ensures a high success rate when performing design migration from lower density devices to higher density devices. in many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a lower density device. however, the exact deta ils of the final resource utilization will impact the likely suc- cess in each case. for more details refer to tn1200, machxo2 density migration .
www.latticesemi.com 3-1 ds1035 dc and switching_01.0 november 2010 advance data sheet ds1035 ? 2010 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. absolute maximum ratings 1, 2, 3 lcmxo2 ze/he (1.2v) lcmxo2 hc (2.5v/3.3v) supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.32v . . . . . . . . . . . . . . . -0.5 to 3.75v supply voltage v ccp . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75v . . . . . . . . . . . . . . . -0.5 to 3.75v output supply voltage v ccio . . . . . . . . . . . . . . . . -0.5 to 3.75v . . . . . . . . . . . . . . . -0.5 to 3.75v i/o tri-state voltage applied . . . . . . . . . . . . . . . . . -0.5 to 3.75v . . . . . . . . . . . . . . . -0.5 to 3.75v dedicated input voltage applied . . . . . . . . . . . . . . -0.5 to 3.75v . . . . . . . . . . . . . . . -0.5 to 4.25v storage temperature (ambient). . . . . . . . . . . . . . -40c to 125c . . . . . . . . . . . . . -40c to 125c junction temperature (t j ) . . . . . . . . . . . . . . . . . . -40c to 125c . . . . . . . . . . . . . -40c to 125c 1. stress above those listed under the ?absolute maximum ra tings? may cause permanent damage to the device. functional operatio n of the device at these or any other conditions abov e those indicated in the operational sectio ns of this specification is not implied. 2. compliance with the lattice thermal management document is required. 3, all voltages referenced to gnd. recommended operating conditions 1 power-on-reset voltage levels 1, 2, 3, 4 symbol parameter min. max. units v cc 1 core supply voltage for 1.2v devices 1.14 1.26 v core supply voltage for 2.5v/3.3v devices 2.375 3.465 v v ccp 1 flash programming supply voltage 3.135 3.465 v v ccio 1, 2 i/o driver supply voltage 1.14 3.465 v t jcom junction temperature commercial operation 0 85 c t jind junction temperature industrial operation -40 100 c 1. like power supplies must be tied together. for example, if v ccio and v cc are both 2.5v, they must also be the same supply. 3.3v v ccio should be tied to v ccp and 1.2v v ccio should be tied to 1.2v v cc respectively. 2. see recommended voltages by i/o standard in subsequent table. symbol parameter min. typ. max. units v porup power-on-reset ramp up trip point (band gap based circuit monitoring v ccint and v ccio ) 0.9 1.02 v v porupext power-on-reset ramp up trip point (band gap based circuit monitoring external v cc power supply) 1.5 2.1 v v pordnbg power-on-reset ramp down trip point (band gap based circuit monitoring v ccint ) 0.9 v v pordnsram power-on-reset ramp down trip point (sram based circuit monitoring v ccint ) 0.6 v 1. these por trip points are onl y provided for guidance. device operation is only characterized for power supply voltages specif ied under rec- ommended operating conditions. 2. for devices without voltage regulators v ccint is the same as the v cc supply voltage. for devices with voltage regulators, v ccint is regu- lated from the v cc supply voltage. 3. note that v porup (min.) and v pordnbg (max.) are in different process cor ners. for any given process corner v pordnbg (max.) is always 12 0mv below v porup (min.). 4. v porupext is for hc devices only. in these devices a separate por circuit monitors the external v cc power supply. machxo2 family data sheet dc and switching characteristics
3-2 dc and switching characteristics lattice semiconductor machxo 2 family data sheet programming/erase specifications hot socketing specifications 1, 2, 3 esd performance lattice qualifies devices per the human body model (h bm) and charged device mode l (cdm). jedec specifica- tions are followed for product qualifications. for more details please refer to the device qualification report. dc electrical characteristics over recommended operating conditions parameter value units ufm maximum erase and reprogram cycles 100,000 cycles configuration flash memory maximum erase and reprogram cycles 10,000 cycles feature row maximum erase and reprogram cycles 1,000 cycles symbol parameter condition max units i dk input or i/o leakage current 0 < v in < v ih (max) +1000 a 1. insensitive to sequence of v cc , v ccp and v ccio . however, assumes monotonic rise/fall rates for v cc , v ccp and v ccio . 2. 0 < v cc < v cc (max), 0 < v ccio < v ccio (max) and 0 < v ccp < v ccp (max). 3. i dk is additive to i pu , i pd or i bh . pin group esd stress min. units all pins hbm 2000 v all pins cdm 500 v symbol parameter condition min. typ. max. units i il , i ih 1, 4 input or i/o leakage 0 < v in < v ccio 10 a v ccio < v in < v ih (max) 175 a i pu i/o active pull-up current 0 < v in < 0.7 v ccio v ccio = 1.2v -30 -230 a 0 < v in < 0.7 v ccio v ccio = 1.5v -30 -207 a 0 < v in < 0.7 v ccio v ccio = 1.8v -30 -309 a 0 < v in < 0.7 v ccio v ccio = 2.5v -30 -156 a 0 < v in < 0.7 v ccio v ccio = 3.3v -30 -246 a i pd i/o active pull-down current v il (max) < v in < v ccio v ccio = 1.2v 30 305 a v il (max) < v in < v ccio v ccio = 1.5v 30 285 a v il (max) < v in < v ccio v ccio = 1.8v 30 242 a v il (max) < v in < v ccio v ccio = 2.5v 30 248 a v il (max) < v in < v ccio v ccio = 3.3v 30 254 a i bhls bus hold low sustaining current v in = v il (max) 30 a
3-3 dc and switching characteristics lattice semiconductor machxo 2 family data sheet i bhhs bus hold high sustaining current v in = 0.7v ccio -30 a i bhlo bus hold low overdrive current 0 ? v in ?? v ccio v ccio = 1.2v 305 a 0 ? v in ?? v ccio v ccio = 1.5v 285 a 0 ? v in ?? v ccio v ccio = 1.8v 242 a 0 ? v in ?? v ccio v ccio = 2.5v 248 a 0 ? v in ?? v ccio v ccio = 3.3v 254 a i bhho bus hold high overdrive current 0 ? v in ?? v ccio v ccio = 1.2v -230 a 0 ? v in ?? v ccio v ccio = 1.5v -207 a 0 ? v in ?? v ccio v ccio = 1.8v -309 a 0 ? v in ?? v ccio v ccio = 2.5v -156 a 0 ? v in ?? v ccio v ccio = 3.3v -246 a v bht 3 bus hold trip points v il (max) v ih (min) v c1 i/o capacitance 2 v ccio = 3.3v, 2.5v, 1.8v, 1.5v, 1.2v, v cc = typ., v io = 0 to v ih (max) 8pf c2 dedicated input capacitance 2 v ccio = 3.3v, 2.5v, 1.8v, 1.5v, 1.2v, v cc = typ., v io = 0 to v ih (max) 8pf v t+ upper voltage threshold 5 v ccio = 3.3v v v ccio = 2.5v v v t- lower voltage threshold 6 v ccio = 3.3v v v ccio = 2.5v v v hyst hysteresis for schmitt trigger inputs 5 v ccio = 3.3v 500 mv v ccio = 2.5v 250 mv 1. input or i/o leakage current is measured wi th the pin configured as an input or as an i/o with the output driver tri-stated. it is not measured with the output driver active. bus maintenance circuits are disabled. 2. t a 25c, f = 1.0mhz. 3. please refer to v il and v ih in the sysio single-ended dc electrical characteristics table of this document. 4. when v ih is higher than v ccio , a transient current typicall y of 30ns in duration or less with a peak current of 6ma can occur on the high-to- low transition. for true lvds output pins in machxo2-1200 and larger devices, v ih must be less than or equal to v ccio . 5. input buffers will not trip high until this threshold is cr ossed. applicable only for lvcmos33 and lvcmos25 inputs. for more details, refer to tn1202, machxo2 sysio usage guide . 6. input buffers will not trip low until this threshold is crossed. applicable only for lvcmos33 and lvcmos25 inputs. for more d etails, refer to tn1202, machxo2 sysio usage guide . symbol parameter condition min. typ. max. units
3-4 dc and switching characteristics lattice semiconductor machxo 2 family data sheet static supply current ? ze devices 1, 2, 3, 6 static power consumption contribu tion of different components ? ? ze devices the table below can be used for approximating static power consumption. for a more accurate power analysis for your design please use the power calculator tool. symbol parameter device typ. 4 units i cc core power supply lcmxo2-256ze 13 a lcmxo2-640ze 23 a lcmxo2-1200ze 44 a lcmxo2-2000ze 61 a lcmxo2-4000ze 97 a lcmxo2-7000ze 148 a i ccp programming power supply v ccp = 3.3v lcmxo2-256ze 0 a lcmxo2-640ze 0 a lcmxo2-1200ze 0 a lcmxo2-2000ze 0 a lcmxo2-4000ze 0 a lcmxo2-7000ze 0 a i ccio bank power supply 5 v ccio = 2.5v all devices ma 1. for further information on suppl y current, please refer to tn1198, power estimation and management for machxo2 devices . 2. assumes user pattern with the following characteristics: al l outputs are tri-stated, all inputs are configured as lvcmos and held at v ccio or gnd, on-chip oscillator is off, on-chip p ll is off. for the impact of turning each of these items on please refer to the follow ing table. 3. frequency = 0 mhz. 4. t j = 25c, power supplies at nominal voltage. 5. does not include pull-up/pull-down. 6. to determine the machxo2 peak start-up cu rrent data, use the power calculator tool. symbol parameter typ. units i dcbg bandgap dc power contribution 75 a i dcpor por dc power contribution 37 a i dcosc oscillator dc power contribution 20 a i dcpll dc power contribution per pll 2450 a i dciobankcontroller dc power contribution per i/o bank controller a i dcplc dc power contribution per plc (50% usage) a
3-5 dc and switching characteristics lattice semiconductor machxo 2 family data sheet static supply current ? hc/he devices 1, 2, 3, 6 symbol parameter device typ. 4 units i cc core power supply lcmxo2-256hc 1070 a lcmxo2-640hc 1470 a lcmxo2-1200hc 2670 a lcmxo2-2000hc 3700 a lcmxo2-4000hc 6300 a lcmxo2-7000hc 9700 a lcmxo2-256he 192 a lcmxo2-640he 385 a lcmxo2-1200he 694 a lcmxo2-2000he 1024 a lcmxo2-4000he 1825 a lcmxo2-7000he 2890 a i ccp programming power supply v ccp = 3.3v lcmxo2-256he/hc 0 a lcmxo2-640he/hc 0 a lcmxo2-1200he/hc 0 a lcmxo2-2000he/hc 0 a lcmxo2-4000he/hc 0 a lcmxo2-7000he/hc 0 a i ccio bank power supply 5 v ccio = 2.5v all devices ma 1. for further information on suppl y current, please refer to tn1198, power estimation and management for machxo2 devices . 2. assumes user pattern = blank with the following characteristics: all outputs are tri-stated, a ll inputs are configured as lv cmos and held at v ccio or gnd, on-chip oscillator is off, on-chip pll is off. 3. frequency = 0 mhz. 4. t j = 25c, power supplies at nominal voltage. 5. does not include pull-up/pull-down. 6. to determine the machxo2 peak start-up cu rrent data, use the power calculator tool.
3-6 dc and switching characteristics lattice semiconductor machxo 2 family data sheet programming and erase flash supply current ? ze devices 1, 2, 3, 4 symbol parameter device typ. 5 units i cc core power supply lcmxo2-256ze ma lcmxo2-640ze ma lcmxo2-1200ze ma lcmxo2-2000ze ma lcmxo2-4000ze ma lcmxo2-7000ze ma i ccp programming power supply lcmxo2-256ze ma lcmxo2-640ze ma lcmxo2-1200ze ma lcmxo2-2000ze ma lcmxo2-4000ze ma lcmxo2-7000ze ma i ccio bank power supply 6 all devices ma 1. for further information on suppl y current, please refer to tn1198, power estimation and management for machxo2 devices . 2. assumes all inputs are held at v ccio or gnd and all outputs are tri-stated. 3. typical user pattern. 4. jtag programming is at 25 mhz. 5. tj = 25c, power supplies at nominal voltage. 6. per bank. v ccio = 2.5v. does not include pull-up/pull-down.
3-7 dc and switching characteristics lattice semiconductor machxo 2 family data sheet programming and erase flash su pply current ? hc/he devices 1, 2, 3, 4 symbol parameter device typ. 5 units i cc core power supply lcmxo2-256hc ma lcmxo2-640hc ma lcmxo2-1200hc ma lcmxo2-2000hc ma lcmxo2-4000hc ma lcmxo2-7000hc ma lcmxo2-256he ma lcmxo2-640he ma lcmxo2-1200he ma lcmxo2-2000he ma lcmxo2-4000he ma lcmxo2-7000he ma i ccp programming power supply lcmxo2-256he/hc ma lcmxo2-640he/hc ma lcmxo2-1200he/hc ma lcmxo2-2000he/hc ma lcmxo2-4000he/hc ma lcmxo2-7000he/hc ma i ccio bank power supply6 all devices ma 1. for further information on suppl y current, please refer to tn1198, power estimation and management for machxo2 devices . 2. assumes all inputs are held at v ccio or gnd and all outputs are tri-stated. 3. typical user pattern. 4. jtag programming is at 25 mhz. 5. t j = 25c, power supplies at nominal voltage. 6. per bank. v ccio = 2.5v. does not include pull-up/pull-down.
3-8 dc and switching characteristics lattice semiconductor machxo 2 family data sheet sysio recommended operating conditions standard v ccio (v) min. typ. max. lvcmos 3.3 3.135 3.3 3.465 lvcmos 2.5 2.375 2.5 2.625 lvcmos 1.8 1.71 1.8 1.89 lvcmos 1.5 1.425 1.5 1.575 lvcmos 1.2 1.14 1.2 1.26 lvttl 3.135 3.3 3.465 pci 3 3.135 3.3 3.465 sstl25 2.375 2.5 2.625 sstl18 1.71 1.8 1.89 hstl18 1.71 1.8 1.89 lv d s 2 5 1, 2 2.375 2.5 2.625 lv d s 3 3 1, 2 3.135 3.3 3.465 lvpecl 1 3.135 3.3 3.465 blvds 1 2.375 2.5 2.625 rsds 1 2.375 2.5 2.625 1. inputs on chip. outputs are implemented with the addition of external resistors. 2. machxo2-1200 and larger devices have dedicated lvds buffers 3. input on the bottom bank of the machxo2-1200 and larger devices only.
3-9 dc and switching characteristics lattice semiconductor machxo 2 family data sheet sysio single-ended dc el ectrical characteristics for more details about mixed mode operation please refer to tn1202, machxo2 sysio usage guide . input/output standard v il v ih v ol max. (v) v oh min. (v) i ol max. 1 (ma) i oh max. 1 (ma) min. (v) max. (v) min. (v) max. (v) lv c m o s 3 . 3 lv t t l -0.3 0.8 2.0 3.6 0.4 v ccio - 0.4 4-4 8-8 12 -12 16 -16 24 -24 0.2 v ccio - 0.2 0.1 -0.1 lvcmos 2.5 -0.3 0.7 1.7 3.6 0.4 v ccio - 0.4 4-4 8-8 12 -12 16 -16 0.2 v ccio - 0.2 0.1 -0.1 lvcmos 1.8 -0.3 0.35v ccio 0.65v ccio 3.6 0.4 v ccio - 0.4 4-4 8-8 12 -12 0.2 v ccio - 0.2 0.1 -0.1 lvcmos 1.5 -0.3 0.35v ccio 0.65v ccio 3.6 0.4 v ccio - 0.4 4-4 8-8 0.2 v ccio - 0.2 0.1 -0.1 lvcmos 1.2 -0.3 0.35v ccio 0.65v ccio 3.6 0.4 v ccio - 0.4 4-2 8-6 0.2 v ccio - 0.2 0.1 -0.1 pci -0.3 0.3v ccio 0.5v ccio 3.6 0.1v ccio 0.9v ccio 1.5 -0.5 sstl25 class i -0.3 v ref - 0.18 v ref + 0.18 3.6 0.54 v ccio - 0.62 8 8 sstl25 class ii -0.3 v ref - 0.18 v ref +0.18 3.6 na na na na sstl18 class i -0.3 v ref - 0.125 v ref +0.125 3.6 0.40 v ccio - 0.40 8 8 sstl18 class ii -0.3 v ref - 0.125 v ref +0.125 3.6 na na na na hstl18 class i -0.3 v ref - 0.1 v ref +0.1 3.6 0.40 v ccio - 0.40 8 8 hstl18 class ii -0.3 v ref - 0.1 v ref +0.1 3.6 na na na na 1. the average dc current drawn by i/os between gnd connections, or between the last gnd in an i/o bank and the end of an i/o ba nk, as shown in the logic signal connections table shall not exceed n * 8ma. where n is the number of i/os betw een bank gnd connection s or between the last gnd in a bank and the end of a bank. 2. machxo2 devices allow lvcmos inputs to be placed in i/o banks where v ccio is different from what is s pecified in the applicable jedec specification. in a majority of cases this operation follows or exceeds the applicable jedec spec ification. the cases where mac hxo2 devices do not meet the relevant jedec specification are documented in the table below. input standard v ccio (v) v il max. (v) lvcmos 33 1.5 0.69 lvcmos 25 1.5 0.69 lvcmos 18 1.5 0.66
3-10 dc and switching characteristics lattice semiconductor machxo 2 family data sheet sysio differential elec trical characteristics the lvds differential output buffers are available on the top side of machxo2-1200 and higher density devices in the machxo2 pld family. lv d s over recommended operating conditions parameter symbol parameter description test conditions min. typ. max. units v inp , v inm input voltage v ccio = 3.3 0 2.4 v v ccio = 2.5 0 2.05 v v thd differential input threshold 100 mv v cm input common mode voltage v ccio = 3.3v 0.05 2.6 v v ccio = 2.5v 0.05 2.0 v i in input current power on 10 a v oh output high voltage for v op or v om r t = 100 ohm 1.375 v v ol output low voltage for v op or v om r t = 100 ohm 0.90 1.025 v v od output voltage differential (v op - v om ), r t = 100 ohm 250 350 450 mv ? v od change in v od between high and low 50 mv v os output voltage offset (v op - v om )/2, r t = 100 ohm 1.125 1.20 1.395 v ? v os change in v os between h and l 50 mv i osd output short circuit current v od = 0v driver outputs shorted 24 ma
3-11 dc and switching characteristics lattice semiconductor machxo 2 family data sheet lvds emulation machxo2 devices can support lvds outputs via emulation (lvds25e), in addition to the lvds support that is available on-chip on certain devices. the output is emulated using complementary lvcmos outputs in conjunc- tion with resistors across the driver outputs on all device s. the scheme shown in figure 3-1 is one possible solu- tion for lvds standard implementation. resistor values in figure 3-1 are industry standard values for 1% resistors. figure 3-1. lvds using external resistors (lvds25e) table 3-1. lvds25e dc conditions over recommended operating conditions parameter description typ. units z out output impedance 20 ohms r s driver series resistor 158 ohms r p driver parallel resistor 140 ohms r t receiver termination 100 ohms v oh output high voltage 1.43 v v ol output low voltage 1.07 v v od output differenti al voltage 0.35 v v cm output common mode voltage 1.25 v z back back impedance 100.5 ohms i dc dc output current 6.03 ma 158 158 zo = 100 140 100 on-chip on-chip off-chip off-chip vccio = 2.5 8ma 8ma note: all resistors are ?%. vccio = 2.5 + - emulated lvds buffer
3-12 dc and switching characteristics lattice semiconductor machxo 2 family data sheet blvds the machxo2 family supports the blvds standard through emulation. the output is emulated using compleme tary lvcmos outputs in conjunction with a parallel external resistor across the driver outputs. the input standard is supported by the lvds differential input buffer on certain devices. blvds is intended for use when multi-drop and bi-directional multi-point differential signaling is required. the scheme shown in figure 3-2 is one possible solution for bi-directional multi-point differential signals. figure 3-2. blvds multi-point output example table 3-2. blvds dc conditions 1 over recommended operating conditions symbol description nominal units zo = 45 zo = 90 z out output impedance 10 10 ohms r s driver series resistance 90 90 ohms r tleft left end termination 45 90 ohms r tright right end termination 45 90 ohms v oh output high voltage 1.376 1.480 v v ol output low voltage 1.124 1.020 v v od output differential voltage 0.253 0.459 v v cm output common mode voltage 1.250 1.250 v i dc dc output current 11.236 10.204 ma 1. for input buffer, see lvds table. heavily loaded backplane, effective zo ~ 45 to 90 ohms differential 2.5v 80 80 80 80 80 80 45-90 ohms 45-90 ohms 80 2.5v 2.5v 2.5v 2.5v 2.5v 2.5v 2.5v + - . . . + - . . . + - + - 16ma 16ma 16ma 16ma 16ma 16ma 16ma 16ma
3-13 dc and switching characteristics lattice semiconductor machxo 2 family data sheet lvpecl the machxo2 family supports the diff erential lvpecl standard through emulation. this output stand ard is emu- lated using complementary lvcmos outputs in conjunction with a parallel resistor across the driver outputs on all the devices. the lvpecl input standard is supported by the lvds differential input buffer on certain devices. the scheme shown in differential l vpecl is one possible solution for point-to-point signals. figure 3-3. diff erential lvpecl table 3-3. lvpecl dc conditions 1 over recommended operating conditions for further information on lvpecl, blvd s and other differential in terfaces please see deta ils of additional techni- cal documentation at the end of the data sheet. symbol description nominal units z out output impedance 10 ohms r s driver series resistor 93 ohms r p driver parallel resistor 196 ohms r t receiver termination 100 ohms v oh output high voltage 2.05 v v ol output low voltage 1.25 v v od output differential voltage 0.80 v v cm output common mode voltage 1.65 v z back back impedance 100.5 ohms i dc dc output current 12.11 ma 1. for input buffer, see lvds table. transmission line, zo = 100 ohm differential 100 ohms 93 ohms 16ma 16ma 93 ohms off-chip on-chip v ccio = 3.3v v ccio = 3.3v + - 196 ohms on-chip off-chip
3-14 dc and switching characteristics lattice semiconductor machxo 2 family data sheet rsds the machxo2 family supports the differential rsds standard. the output standard is emulated using complemen- tary lvcmos outputs in conjunction with a parallel resistor across the driver outputs on all the devices. the rsds input standard is supported by the lvds differential input buffer on certain devices. the scheme shown in figure 3- 4 is one possible solution for rsds standard implementation. use lvds25e mode with suggested resistors for rsds operation. resistor values in figure 3-4 are industry standard values for 1% resistors. figure 3-4. rsds (reduced swing differential standard) table 3-4. rsds dc conditions parameter description typical units z out output impedance 20 ohms r s driver series resistor 294 ohms r p driver parallel resistor 121 ohms r t receiver termination 100 ohms v oh output high voltage 1.35 v v ol output low voltage 1.15 v v od output differential voltage 0.20 v v cm output common mode voltage 1.25 v z back back impedance 101.5 ohms i dc dc output current 3.66 ma 100 294 294 on-chip on-chip off-chip emulated rsds buffer vccio = 2.5v vccio = 2.5v 8ma 8ma zo = 100 + - 121 off-chip
3-15 dc and switching characteristics lattice semiconductor machxo 2 family data sheet typical building block function performance ? hc/he devices 1 pin-to-pin performance (lvcmos25 12ma drive) register-to-register performance function -6 timing units basic functions 16-bit decoder 8.8 ns 4:1 mux 7.6 ns 16:1 mux 8.5 ns function -6 timing units basic functions 16:1 mux 386 mhz 16-bit adder 256 mhz 16-bit counter 294 mhz 64-bit counter 146 mhz embedded memory functions 1024x9 true-dual port ram (write through or normal, ebr output registers) 183 mhz distributed memory functions 16x4 pseudo-dual port ram (one pfu) 451 mhz 1. the above timing numbers are generated using the isplever design tool. exact performance may vary with device and tool version. the tool uses inter nal parameters that have been characterized but are not tested on every device.
3-16 dc and switching characteristics lattice semiconductor machxo 2 family data sheet typical building block function performance ? ze devices 1 pin-to-pin performance (lvcmos25 12ma drive) register-to-register performance derating logic timing logic timing provided in the following sections of the data sheet and the lattice design tools are worst case num- bers in the operating range. actual delays may be much faster. lattice design tools can provide logic timing num- bers at a particular temperature and voltage. function -3 timing units basic functions 16-bit decoder 14.8 ns 4:1 mux 12.1 ns 16:1 mux 13.5 ns function -3 timing units basic functions 16:1 mux 160 mhz 16-bit adder 121 mhz 16-bit counter 135 mhz 64-bit counter 70 mhz embedded memory functions 1024x9 true-dual port ram (write through or normal, ebr output registers) 123 mhz distributed memory functions 16x4 pseudo-dual port ram (one pfu) mhz 1. the above timing numbers are generated using the isplever design tool. exact performance may vary with device and tool version. the tool uses inter nal parameters that have been characterized but are not tested on every device.
3-17 dc and switching characteristics lattice semiconductor machxo 2 family data sheet machxo2 external switching ch aracteristics ? hc/he devices 1 over recommended operating conditions parameter description device -6 -5 -4 units min. max. min. max. min. max. pin-lut-pin propagation delay t pd best case propagation delay through one lut-4 machxo2-256 ? 6.80 ? 7.05 ? 7.36 ns machxo2-640 ? 7.16 ? 7.47 ? 7.82 ns machxo2-1200 ? 7.33 ? 7.66 ? 8.03 ns machxo2-2000 ? 7.35 ? 7.69 ? 8.07 ns machxo2-4000 ? 7.33 ? 7.66 ? 8.05 ns machxo2-7000 ? 7.33 ? 7.66 ? 8.03 ns general i/o pin parameters (using primary clock without pll) 1 t co clock to output - pio output register machxo2-256 ? 7.22 ? 7.51 ? 7.79 ns machxo2-640 ? 7.26 ? 7.54 ? 7.83 ns machxo2-1200 ? 7.57 ? 7.89 ? 8.21 ns machxo2-2000 ? 7.59 ? 7.90 ? 8.22 ns machxo2-4000 ? 7.83 ? 8.15 ? 8.47 ns machxo2-7000 ? 7.73 ? 8.06 ? 8.38 ns t su clock to data setup - pio input register machxo2-256 -1.02 ? -1.15 ? -1.28 ? ns machxo2-640 -1.05 ? -1.18 ? -1.32 ? ns machxo2-1200 -1.35 ? -1.51 ? -1.67 ? ns machxo2-2000 -1.36 ? -1.52 ? -1.68 ? ns machxo2-4000 -1.24 ? -1.40 ? -1.57 ? ns machxo2-7000 -1.54 ? -1.71 ? -1.89 ? ns t h clock to data hold - pio input register machxo2-256 1.48 ? 1.64 ? 1.80 ? ns machxo2-640 1.52 ? 1.68 ? 1.84 ? ns machxo2-1200 1.83 ? 2.03 ? 2.22 ? ns machxo2-2000 1.85 ? 2.04 ? 2.23 ? ns machxo2-4000 1.75 ? 1.95 ? 2.14 ? ns machxo2-7000 2.03 ? 2.23 ? 2.43 ? ns t su_del clock to data setup - pio input register with data input delay machxo2-256 2.96 ? 3.12 ? 3.29 ? ns machxo2-640 2.93 ? 3.09 ? 3.25 ? ns machxo2-1200 2.63 ? 2.77 ? 2.90 ? ns machxo2-2000 2.62 ? 2.76 ? 2.89 ? ns machxo2-4000 2.74 ? 2.87 ? 3.00 ? ns machxo2-7000 2.44 ? 2.56 ? 2.68 ? ns t h_del clock to data hold - pio input register with input data delay machxo2-256 -2.50 ? -2.63 ? -2.77 ? ns machxo2-640 -2.46 ? -2.59 ? -2.73 ? ns machxo2-1200 -2.14 ? -2.25 ? -2.35 ? ns machxo2-2000 -2.13 ? -2.23 ? -2.34 ? ns machxo2-4000 -2.23 ? -2.33 ? -2.43 ? ns machxo2-7000 -1.95 ? -2.04 ? -2.14 ? ns f max_io clock frequency of i/o and pfu register all machxo2 devices ? ? ? mhz
3-18 dc and switching characteristics lattice semiconductor machxo 2 family data sheet general i/o pin parameters (using edge clock without pll) 1 t coe clock to output - pio output register machxo2-1200 ? 6.63 ? 6.88 ? 7.12 ns machxo2-2000 ? 7.40 ? 7.73 ? 8.07 ns machxo2-4000 ? 7.40 ? 7.73 ? 8.07 ns machxo2-7000 ? 6.63 ? 6.88 ? 7.12 ns t sue clock to data setup - pio input register machxo2-1200 -0.49 ? -0.58 ? -0.68 ? ns machxo2-2000 -1.13 ? -1.28 ? -1.43 ? ns machxo2-4000 -1.13 ? -1.28 ? -1.43 ? ns machxo2-7000 -0.49 ? -0.58 ? -0.68 ? ns t he clock to data hold - pio input register machxo2-1200 0.93 ? 1.05 ? 1.16 ? ns machxo2-2000 1.66 ? 1.86 ? 2.09 ? ns machxo2-4000 1.66 ? 1.86 ? 2.09 ? ns machxo2-7000 0.93 ? 1.05 ? 1.16 ? ns t su_dele clock to data setup - pio input register with data input delay machxo2-1200 -0.49 ? -0.58 ? -0.68 ? ns machxo2-2000 -1.13 ? -1.28 ? -1.43 ? ns machxo2-4000 -1.13 ? -1.28 ? -1.43 ? ns machxo2-7000 -0.49 ? -0.58 ? -0.68 ? ns t h_dele clock to data hold - pio input register with input data delay machxo2-1200 0.93 ? 1.05 ? 1.16 ? ns machxo2-2000 1.66 ? 1.86 ? 2.09 ? ns machxo2-4000 1.66 ? 1.86 ? 2.09 ? ns machxo2-7000 0.93 ? 1.05 ? 1.16 ? ns f max_ioe clock frequency of i/o and pfu register all machxo2 devices ? ? ? mhz general i/o pin parameters (using primary clock with pll) 1 t copll clock to output - pio output register machxo2-1200 ? 7.00 ? 7.22 ? 7.45 ns machxo2-2000 ? 6.93 ? 7.14 ? 7.36 ns machxo2-4000 ? 7.45 ? 7.74 ? 8.04 ns machxo2-7000 ? 7.04 ? 7.27 ? 7.52 ns t supll clock to data setup - pio input register machxo2-1200 -0.61 ? -0.67 ? -0.72 ? ns machxo2-2000 -0.54 ? -0.60 ? -0.66 ? ns machxo2-4000 -0.98 ? -1.11 ? -1.23 ? ns machxo2-7000 -0.64 ? -0.72 ? -0.78 ? ns t hpll clock to data hold - pio input register machxo2-1200 1.12 ? 1.21 ? 1.32 ? ns machxo2-2000 1.05 ? 1.13 ? 1.23 ? ns machxo2-4000 1.57 ? 1.73 ? 1.91 ? ns machxo2-7000 1.16 ? 1.26 ? 1.39 ? ns t su_delpll clock to data setup - pio input register with data input delay machxo2-1200 -0.61 ? -0.67 ? -0.72 ? ns machxo2-2000 -0.54 ? -0.60 ? -0.66 ? ns machxo2-4000 -0.98 ? -1.11 ? -1.23 ? ns machxo2-7000 -0.64 ? -0.72 ? -0.78 ? ns t h_delpll clock to data hold - pio input register with input data delay machxo2-1200 1.12 ? 1.21 ? 1.32 ? ns machxo2-2000 1.05 ? 1.13 ? 1.23 ? ns machxo2-4000 1.57 ? 1.73 ? 1.91 ? ns machxo2-7000 1.16 ? 1.26 ? 1.39 ? ns parameter description device -6 -5 -4 units min. max. min. max. min. max.
3-19 dc and switching characteristics lattice semiconductor machxo 2 family data sheet generic ddrx1 inputs with cl ock and data aligned at pin ? (gddrx1_rx.sclk.aligned) using pclk pin for clock input generic ddrx1 inputs with cloc k and data ce ntered at pin ? (gddrx1_rx.sclk.centered) us ing pclk pin for clock input generic ddrx2 inputs with cl ock and data aligned at pin ? (gddrx2_rx.eclk.aligned) using pclk pin for clock input generic ddrx2 inputs with cloc k and data ce ntered at pin ? (gddrx2_rx.eclk.centered) us ing pclk pin for clock input parameter description device hc/he devices units -6 -5 -4 t dva input data valid after clk all machxo2 devices, all sides max. 0.188 0.204 0.22 ui t dve input data hold after clk min. 0.25 0.25 0.25 ui f data ddrx1 input data speed max. 568.18 491.4 432.9 mbps f ddrx1 ddrx1 sclk frequency max. 284.09 245.7 216.45 mhz parameter description device hc/he devices units -6 -5 -4 t su input data setup before clk all machxo2 devices, all sides min. 0.77 0.76 0.76 ns t ho input data hold after clk min. 0.22 0.22 0.22 ns f data ddrx1 input data speed max. 568.18 491.4 432.9 mbps f ddrx1 ddrx1 sclk frequency max. 284.09 245.7 216.45 mhz parameter description device hc/he devices units -6 -5 -4 t dva input data valid after clk machxo2-1200 and larger devices, bottom side only max. ui t dve input data hold after clk min. ui f data ddrx2 serial input data speed max. 606.06 505.05 432.9 mbps f ddrx2 ddrx2 eclk frequency max. 303.03 252.53 216.45 mhz f sclk sclk frequency max. 151.52 126.26 108.23 mhz parameter description device hc/he devices units -6 -5 -4 t su input data setup before clk machxo2-1200 and larger devices, bottom side only min. 0.36 0.36 0.36 ns t ho input data hold after clk min. 0.08 0.08 0.08 ns f data ddrx2 serial input data speed max. 606.06 505.05 432.9 mbps f ddrx2 ddrx2 eclk frequency max. 303.03 252.53 216.45 mhz f sclk sclk frequency max. 151.52 126.26 108.23 mhz
3-20 dc and switching characteristics lattice semiconductor machxo 2 family data sheet generic ddrx4 inputs with cl ock and data aligned at pin ? (gddrx4_rx.eclk.aligned) using pclk pin for clock input generic ddrx4 inputs with cloc k and data ce ntered at pin ? (gddrx4_rx.eclk.centered) us ing pclk pin for clock input 7:1 lvds inputs (gddr71_rx.eclk.7:1) generic ddr outputs with cl ock and data aligned at pin ? (gddrx1_tx.sclk.aligned) usin g pclk pin for clock input parameter description device hc/he devices units -6 -5 -4 t dva input data valid after eclk machxo2-1200 and larger devices, bottom side only max. ui t dve input data hold after eclk min. ui f data ddrx4 serial input data speed max. 727.27 596.3 505.05 mbps f ddrx4 ddrx4 eclk frequency max. 363.64 298.15 252.53 mhz f sclk sclk frequency max. 90.91 74.54 63.13 mhz parameter description device hc/he devices units -6 -5 -4 t su input data setup before eclk machxo2-1200 and larger devices, bottom side only min. 0.36 0.36 0.36 ns t ho input data hold after eclk min. 0.08 0.08 0.08 ns f data ddrx4 serial input data speed max. 727.27 596.3 505.05 mbps f ddrx4 ddrx4 eclk frequency max. 363.64 298.15 252.53 mhz f sclk sclk frequency max. 90.91 74.54 63.13 mhz parameter description device hc/he devices units -6 -5 -4 t rpbi rx input strobe position for bit machxo2-1200 and larger devices, bottom side only min. ns ?i? (?i? = 0 to 6) max. ns t b serial input data bit time min. 1.38 1.68 1.98 ns f data ddr71 serial input data speed max. 727.27 596.3 505.05 mbps min. 70 70 70 mbps f ddr71 ddr71 eclk frequency max. 363.64 298.15 252.53 mhz min. 35 35 35 mhz f clkin 7:1 input clock frequency (sclk) (minimum limited by pll) max. 103.9 85.19 72.15 mhz min. 10 10 10 mhz t rpb0_min rx strobe position for bit ?0?, min. ns t rpb0_max (0.292ui, 0.708ui) max. ns parameter description device hc/he devices units -6 -5 -4 t dia output data invalid after clk output all machxo2 devices, all sides max. ns t dib output data invalid before clk output max. ns f data ddrx1 output data speed max. 568.18 491.4 432.9 mbps f ddrx1 ddrx1 sclk frequency max. 284.09 245.7 216.45 mhz
3-21 dc and switching characteristics lattice semiconductor machxo 2 family data sheet generic ddr outputs with cloc k and data ce ntered at pin ? (gddrx1_tx.sclk.centered) us ing pclk pin for clock input generic ddrx2 outputs with cl ock and data aligned at pin ? (gddrx2_tx.eclk.aligned) usin g pclk pin for clock input generic ddrx2 outputs with cl ock and data centered at pin ? (gddrx2_tx.eclk.centered) us ing pclk pin for clock input generic ddrx4 outputs with cl ock and data aligned at pin ? (gddrx4_tx.eclk.aligned) usin g pclk pin for clock input parameter description device hc/he devices units -6 -5 -4 t dvb output data valid before clk output all machxo2 devices, all sides max. 0.25 0.25 0.25 ui t dva output data valid after clk output min. 0.25 0.25 0.25 ui f data ddrx1 output data speed max. 568.18 491.4 432.9 mbps min. mbps f ddrx1 ddrx1 sclk frequency (minimum limited by pll) max. 284.09 245.7 216.45 mhz min. mhz parameter description device hc/he devices units -6 -5 -4 t dia output data invalid after clk output machxo2-1200 and larger devices, top side only max. ns t dib output data invalid before clk output max. ns f data ddrx2 serial output data speed max. 606.06 505.05 432.9 mbps f ddrx2 ddrx2 eclk frequency max. 303.03 252.53 216.45 mhz f sclk sclk frequency max. 151.52 126.26 108.23 mhz parameter description device hc/he devices units -6 -5 -4 t dvb output data valid before clk output machxo2-1200 and larger devices, top side only max. 0.25 0.25 0.25 ui t dva output data valid after clk output min. 0.25 0.25 0.25 ui f data ddrx2 serial output data speed max. 606.06 505.05 432.9 mbps min. mbps f ddrx2 ddrx2 eclk frequency (minimum limited by pll) max. 303.03 252.53 216.45 mhz min. mhz f sclk sclk frequency max. 151.52 126.26 108.23 mhz parameter description device hc/he devices units -6 -5 -4 t dia output data invalid after clk output machxo2-1200 and larger devices, top side only max. ns t dib output data invalid before clk output max. ns f data ddrx4 serial output data speed max. 727.27 599.88 505.05 mbps f ddrx4 ddrx4 eclk frequency max. 363.64 299.94 252.53 mhz f sclk sclk frequency max. 90.91 74.99 63.13 mhz
3-22 dc and switching characteristics lattice semiconductor machxo 2 family data sheet generic ddrx4 outputs with cl ock and data centered at pin ? (gddrx4_tx.eclk.centered) us ing pclk pin for clock input 7:1 lvds outputs (gddr71_tx.eclk.7:1) ddr, ddr2 and lpddr parameter description device hc/he devices units -6 -5 -4 t dvb output data valid before clk output machxo2-1200 and larger devices, top side only max. 0.25 0.25 0.25 ui t dva output data valid after clk output min. 0.25 0.25 0.25 ui f data ddrx4 serial output data speed max. 727.27 599.88 505.05 mbps min. mbps f ddrx4 ddrx4 eclk frequency (minimum limited by pll) max. 363.64 299.94 252.53 mhz min. mhz f sclk sclk frequency max. 90.91 74.99 63.13 mhz parameter description device hc/he devices units -6 -5 -4 t tpbi tx output pulse position for bit ?i?, ?i? = 0 to 6. machxo2-1200 and larger devices, top side only. min. ns max. ns t b serial output data bit time min. 1.38 1.67 1.98 ns f data ddr71 serial output data speed max. 727.27 599.88 505.05 mbps min. 70 70 70 mbps f ddr71 ddr71 eclk frequency max. 363.64 299.94 252.53 mhz min. 35 35 35 mhz f clkout 7:1 output clock frequency (sclk) (minimum limited by pll) max. 103.9 85.7 72.15 mhz min. 10 10 10 mhz parameter description device hc/he devices units -6 -5 -4 t dvadq input data valid after dqs input machxo2-1200 and larger devices, right side only. max. ui t dvedq input data hold after dqs input min. ui t dqvbs output data invalid before dqs output min. ui t dqvas output data invalid after dqs output min. ui f data mem ddr serial data speed max. 568.18 491.4 432.9 mbps f max_ddr ddr clock maximum frequency max. 284.09 245.7 216.45 mhz f min_ddr lpddr min. frequency min. 0 0 0 mhz mem ddr2 min. frequency min. 83.33 83.33 83.33 mhz mem ddr min. frequency min. 125 125 125 mhz non-mem ddr min. frequency min. 0 0 0 mhz
3-23 dc and switching characteristics lattice semiconductor machxo 2 family data sheet notes: 1. commercial timing numbers are shown. industrial numb ers are typically slower and can be extracted from the lattice design tools. timing in range 0c to 85c shown, please consult software for timing outside this range. 2. general i/o timing numbers based on lvcmos 2.5, 8ma, 0pf load. 3. generic ddr timing numbers based on lvds i/o. 4. ddr timing numbers based on sstl25. ddr2 timing numbers based on sstl18. lpddr timing numbers based in lvcmos18. 5. 7:1 lvds (gddr71) uses the 1lvds i/o standard. 6. for generic ddrx1 mode t su = t ho = (t dve - t dva - 0.03ns)/2. parameter description device hc/he devices units -6 -5 -4 t dvadq input data valid after dqs input machxo2-1200 and larger devices, right side only. max. ui t dvedq input data hold after dqs input min. ui t dqvbs output dq data valid before dqs min. ui t dqvas output dq data valid after dqs min. ui f data mem ddr serial data speed max. mbps f sclk sclk frequency max. mhz f mem_ddr mem ddr frequency max. mbps min. mbps f mem_ddr2 mem ddr2 frequency max. mbps min. mbps f lpddr lpddr frequency max. mbps min. mbps
3-24 dc and switching characteristics lattice semiconductor machxo 2 family data sheet machxo2 external switching characteristics ? ze devices 1 over recommended operating conditions parameter description device -3 -2 -1 units min. max. min. max. min. max. pin-lut-pin propagation delay t pd best case propagation delay through one lut-4 machxo2-256 ? 9.77 ? 10.25 ? 10.72 ns machxo2-640 ? 10.27 ? 10.81 ? 11.35 ns machxo2-1200 ? 10.27 ? 10.81 ? 11.35 ns machxo2-2000 ? 10.31 ? 10.85 ? 11.39 ns machxo2-4000 ? 10.96 ? 11.57 ? 12.17 ns machxo2-7000 ? 10.29 ? 10.83 ? 11.38 ns general i/o pin parameters (usi ng primary clock without pll) 1 t co clock to output - pio output register machxo2-256 ? 10.69 ? 11.26 ? 11.82 ns machxo2-640 ? 10.78 ? 11.35 ? 11.93 ns machxo2-1200 ? 11.05 ? 11.67 ? 12.28 ns machxo2-2000 ? 11.08 ? 11.70 ? 12.31 ns machxo2-4000 ? 11.15 ? 11.80 ? 12.45 ns machxo2-7000 ? 11.39 ? 12.03 ? 12.67 ns t su clock to data setup - pio input register machxo2-256 -2.88 ? -3.18 ? -3.48 ? ns machxo2-640 -2.95 ? -3.25 ? -3.56 ? ns machxo2-1200 -3.21 ? -3.55 ? -3.88 ? ns machxo2-2000 -3.23 ? -3.57 ? -3.90 ? ns machxo2-4000 -3.30 ? -3.67 ? -4.05 ? ns machxo2-7000 -3.65 ? -4.02 ? -4.38 ? ns t h clock to data hold - pio input register machxo2-256 3.46 ? 3.77 ? 4.09 ? ns machxo2-640 3.54 ? 3.87 ? 4.19 ? ns machxo2-1200 3.82 ? 4.18 ? 4.55 ? ns machxo2-2000 3.85 ? 4.21 ? 4.58 ? ns machxo2-4000 3.91 ? 4.32 ? 4.72 ? ns machxo2-7000 4.22 ? 4.61 ? 5.00 ? ns t su_del clock to data setup - pio input register with data input delay machxo2-256 3.72 ? 3.99 ? 4.24 ? ns machxo2-640 3.66 ? 3.92 ? 4.16 ? ns machxo2-1200 3.39 ? 3.63 ? 3.84 ? ns machxo2-2000 3.37 ? 3.61 ? 3.82 ? ns machxo2-4000 3.69 ? 3.89 ? 4.06 ? ns machxo2-7000 2.99 ? 3.20 ? 3.37 ? ns t h_del clock to data hold - pio input register with input data delay machxo2-256 -3.15 ? -3.40 ? -3.63 ? ns machxo2-640 -3.06 ? -3.31 ? -3.52 ? ns machxo2-1200 -2.79 ? -3.00 ? -3.17 ? ns machxo2-2000 -2.76 ? -2.97 ? -3.14 ? ns machxo2-4000 -3.04 ? -3.21 ? -3.35 ? ns machxo2-7000 -2.41 ? -2.59 ? -2.74 ? ns f max_io clock frequency of i/o and pfu register all machxo2 devices ? ? ? mhz
3-25 dc and switching characteristics lattice semiconductor machxo 2 family data sheet general i/o pin parameters (using edge clock without pll) 1 t coe clock to output - pio output register machxo2-1200 ? 9.35 ? 9.78 ? 10.21 ns machxo2-2000 ? 11.18 ? 11.78 ? 12.38 ns machxo2-4000 ? 11.18 ? 11.78 ? 12.38 ns machxo2-7000 ? 9.35 ? 9.78 ? 10.21 ns t sue clock to data setup - pio input register machxo2-1200 -1.44 ? -1.57 ? -1.69 ? ns machxo2-2000 -2.78 ? -3.02 ? -3.25 ? ns machxo2-4000 -2.78 ? -3.02 ? -3.25 ? ns machxo2-7000 -1.44 ? -1.57 ? -1.69 ? ns t he clock to data hold - pio input register machxo2-1200 2.18 ? 2.36 ? 2.54 ? ns machxo2-2000 3.94 ? 4.29 ? 4.64 ? ns machxo2-4000 3.94 ? 4.29 ? 4.64 ? ns machxo2-7000 2.18 ? 2.36 ? 2.54 ? ns t su_dele clock to data setup - pio input register with data input delay machxo2-1200 -1.44 ? -1.57 ? -1.69 ? ns machxo2-2000 -2.78 ? -3.02 ? -3.25 ? ns machxo2-4000 -2.78 ? -3.02 ? -3.25 ? ns machxo2-7000 -1.44 ? -1.57 ? -1.69 ? ns t h_dele clock to data hold - pio input register with input data delay machxo2-1200 2.18 ? 2.36 ? 2.54 ? ns machxo2-2000 3.94 ? 4.29 ? 4.64 ? ns machxo2-4000 3.94 ? 4.29 ? 4.64 ? ns machxo2-7000 2.18 ? 2.36 ? 2.54 ? ns f max_ioe clock frequency of i/o and pfu register all machxo2 devices ? ? ? mhz general i/o pin parameters (u sing primary clock with pll) 1 t copll clock to output - pio output register machxo2-1200 ? 9.92 ? 10.36 ? 10.79 ns machxo2-2000 ? 9.72 ? 10.14 ? 10.56 ns machxo2-4000 ? 10.87 ? 11.40 ? 11.93 ns machxo2-7000 ? 9.98 ? 10.41 ? 10.84 ns t supll clock to data setup - pio input register machxo2-1200 -1.60 ? -1.73 ? -1.86 ? ns machxo2-2000 -1.44 ? -1.56 ? -1.68 ? ns machxo2-4000 -2.34 ? -2.52 ? -2.69 ? ns machxo2-7000 -1.65 ? -1.79 ? -1.92 ? ns t hpll clock to data hold - pio input register machxo2-1200 2.49 ? 2.67 ? 2.86 ? ns machxo2-2000 2.29 ? 2.46 ? 2.63 ? ns machxo2-4000 3.41 ? 3.69 ? 3.97 ? ns machxo2-7000 2.55 ? 2.73 ? 2.91 ? ns t su_delpll clock to data setup - pio input register with data input delay machxo2-1200 -1.60 ? -1.73 ? -1.86 ? ns machxo2-2000 -1.44 ? -1.56 ? -1.68 ? ns machxo2-4000 -2.34 ? -2.52 ? -2.69 ? ns machxo2-7000 -1.65 ? -1.79 ? -1.92 ? ns t h_delpll clock to data hold - pio input register with input data delay machxo2-1200 2.49 ? 2.67 ? 2.86 ? ns machxo2-2000 2.29 ? 2.46 ? 2.63 ? ns machxo2-4000 3.41 ? 3.69 ? 3.97 ? ns machxo2-7000 2.55 ? 2.73 ? 2.91 ? ns parameter description device -3 -2 -1 units min. max. min. max. min. max.
3-26 dc and switching characteristics lattice semiconductor machxo 2 family data sheet generic ddrx1 inputs with cl ock and data aligned at pin ? (gddrx1_rx.sclk.aligned) using pclk pin for clock input generic ddrx1 inputs with cloc k and data ce ntered at pin ? (gddrx1_rx.sclk.centered) us ing pclk pin for clock input generic ddrx2 inputs with cl ock and data aligned at pin ? (gddrx2_rx.eclk.aligned) using pclk pin for clock input generic ddrx2 inputs with cloc k and data ce ntered at pin ? (gddrx2_rx.eclk.centered) us ing pclk pin for clock input parameter description device ze devices units -6 -5 -4 t dva input data valid after clk all machxo2 devices, all sides max. 0.188 0.204 0.22 ui t dve input data hold after clk min. 0.25 0.25 0.25 ui f data ddrx1 input data speed max. 568.18 491.4 432.9 mbps f ddrx1 ddrx1 sclk frequency max. 284.09 245.7 216.45 mhz parameter description device ze devices units -6 -5 -4 t su input data setup before clk all machxo2 devices, all sides min. 0.77 0.76 0.76 ns t ho input data hold after clk min. 0.22 0.22 0.22 ns f data ddrx1 input data speed max. 568.18 491.4 432.9 mbps f ddrx1 ddrx1 sclk frequency max. 284.09 245.7 216.45 mhz parameter description device ze devices units -6 -5 -4 t dva input data valid after clk machxo2-1200 and larger devices, bottom side only max. ui t dve input data hold after clk min. ui f data ddrx2 serial input data speed max. 606.06 505.05 432.9 mbps f ddrx2 ddrx2 eclk frequency max. 303.03 252.53 216.45 mhz f sclk sclk frequency max. 151.52 126.26 108.23 mhz parameter description device ze devices units -6 -5 -4 t su input data setup before clk machxo2-1200 and larger devices, bottom side only min. 0.36 0.36 0.36 ns t ho input data hold after clk min. 0.08 0.08 0.08 ns f data ddrx2 serial input data speed max. 606.06 505.05 432.9 mbps f ddrx2 ddrx2 eclk frequency max. 303.03 252.53 216.45 mhz f sclk sclk frequency max. 151.52 126.26 108.23 mhz
3-27 dc and switching characteristics lattice semiconductor machxo 2 family data sheet generic ddrx4 inputs with cl ock and data aligned at pin ? (gddrx4_rx.eclk.aligned) using pclk pin for clock input generic ddrx4 inputs with cloc k and data ce ntered at pin ? (gddrx4_rx.eclk.centered) us ing pclk pin for clock input 7:1 lvds inputs (gddr71_rx.eclk.7:1) generic ddr outputs with cl ock and data aligned at pin ? (gddrx1_tx.sclk.aligned) usin g pclk pin for clock input parameter description device ze devices units -6 -5 -4 t dva input data valid after eclk machxo2-1200 and larger devices, bottom side only max. ui t dve input data hold after eclk min. ui f data ddrx4 serial input data speed max. 727.27 596.3 505.05 mbps f ddrx4 ddrx4 eclk frequency max. 363.64 298.15 252.53 mhz f sclk sclk frequency max. 90.91 74.54 63.13 mhz parameter description device ze devices units -6 -5 -4 t su input data setup before eclk machxo2-1200 and larger devices, bottom side only min. 0.36 0.36 0.36 ns t ho input data hold after eclk min. 0.08 0.08 0.08 ns f data ddrx4 serial input data speed max. 727.27 596.3 505.05 mbps f ddrx4 ddrx4 eclk frequency max. 363.64 298.15 252.53 mhz f sclk sclk frequency max. 90.91 74.54 63.13 mhz parameter description device ze devices units -6 -5 -4 t rpbi rx input strobe position for bit machxo2-1200 and larger devices, bottom side only min. ns ?i? (?i? = 0 to 6) max. ns t b serial input data bit time min. 1.38 1.68 1.98 ns f data ddr71 serial input data speed max. 727.27 596.3 505.05 mbps min. 70 70 70 mbps f ddr71 ddr71 eclk frequency max. 363.64 298.15 252.53 mhz min. 35 35 35 mhz f clkin 7:1 input clock frequency (sclk) max. 103.9 85.19 72.15 mhz (minimum limited by pll) min. 10 10 10 mhz t rpb0_min rx strobe position for bit ?0?, min. ns t rpb0_max (0.292ui, 0.708ui) max. ns parameter description device ze devices units -6 -5 -4 t dia output data invalid after clk output all machxo2 devices, all sides max. ns t dib output data invalid before clk max. ns output f data ddrx1 output data speed max. 568.18 491.4 432.9 mbps f ddrx1 ddrx1 sclk frequency max. 284.09 245.7 216.45 mhz
3-28 dc and switching characteristics lattice semiconductor machxo 2 family data sheet generic ddr outputs with cloc k and data ce ntered at pin ? (gddrx1_tx.sclk.centered) us ing pclk pin for clock input generic ddrx2 outputs with cl ock and data aligned at pin ? (gddrx2_tx.eclk.aligned) usin g pclk pin for clock input generic ddrx2 outputs with cl ock and data centered at pin ? (gddrx2_tx.eclk.centered) us ing pclk pin for clock input generic ddrx4 outputs with cl ock and data aligned at pin ? (gddrx4_tx.eclk.aligned) usin g pclk pin for clock input parameter description device ze devices units -6 -5 -4 t dvb output data valid before clk output all machxo2 devices, all sides max. ui t dva output data valid after clk output min. ui f data ddrx1 output data speed max. 568.18 491.4 432.9 mbps min. mbps f ddrx1 ddrx1 sclk frequency max. 284.09 245.7 216.45 mhz (minimum limited by pll) min. mhz parameter description device ze devices units -6 -5 -4 t dia output data invalid after clk output machxo2-1200 and larger devices, top side only max. ns t dib output data invalid before clk output max. ns f data ddrx2 serial output data speed max. 606.06 505.05 432.9 mbps f ddrx2 ddrx2 eclk frequency max. 303.03 252.53 216.45 mhz f sclk sclk frequency max. 151.52 126.26 108.23 mhz parameter description device ze devices units -6 -5 -4 t dvb output data valid before clk output machxo2-1200 and larger devices, top side only max. ui t dva output data valid after clk output min. ui f data ddrx2 serial output data speed max. 606.06 505.05 432.9 mbps min. mbps f ddrx2 ddrx2 eclk frequency max. 303.03 252.53 216.45 mhz (minimum limited by pll) min. mhz f sclk sclk frequency max. 151.52 126.26 108.23 mhz parameter description device ze devices units -6 -5 -4 t dia output data invalid after clk output machxo2-1200 and larger devices, top side only max. ns t dib output data invalid before clk output max. ns f data ddrx4 serial output data speed max. 727.27 599.88 505.05 mbps f ddrx4 ddrx4 eclk frequency max. 363.64 299.94 252.53 mhz f sclk sclk frequency max. 90.91 74.99 63.13 mhz
3-29 dc and switching characteristics lattice semiconductor machxo 2 family data sheet generic ddrx4 outputs with cl ock and data centered at pin ? (gddrx4_tx.eclk.centered) us ing pclk pin for clock input 7:1 lvds outputs (gddr71_tx.eclk.7:1) ddr, ddr2 and lpddr parameter description device ze devices units -6 -5 -4 t dvb output data valid before clk output machxo2-1200 and larger devices, top side only max. ui t dva output data valid after clk output min. ui f data ddrx4 serial output data speed max. 727.27 599.88 505.05 mbps min. mbps f ddrx4 ddrx4 eclk frequency (minimum limited by pll) max. 363.64 299.94 252.53 mhz min. f sclk sclk frequency max. 90.91 74.99 63.13 mhz parameter description device ze devices units -6 -5 -4 t tpbi tx output pulse position for bit ?i?, machxo2-1200 and larger devices, top side only min. ns ?i? = 0 to 6. max. ns t b serial output data bit time min. 1.38 1.67 1.98 ns f data ddr71 serial output data speed max. 727.27 599.88 505.05 mbps min. 70 70 70 mbps f ddr71 ddr71 eclk frequency max. 363.64 299.94 252.53 mhz min. 35 35 35 mhz f clkout 7:1 output clock frequency (sclk) (minimum limited by pll) max. 103.9 85.7 72.15 mhz min. 10 10 10 mhz parameter description device ze devices units -6 -5 -4 t dvadq input data valid after dqs input machxo2-1200 and larger devices, right side only max. ui t dvedq input data hold after dqs input min. ui t dqvbs output data invalid before dqs output min. ui t dqvas output data invalid after dqs output min. ui f data mem ddr serial data speed max. 568.18 491.4 432.9 mbps f max_ddr ddr clock maximum frequency max. 284.09 245.7 216.45 mhz f min_ddr lpddr min. frequency min. 0 0 0 mhz mem ddr2 min. frequency min. 83.33 83.33 83.33 mhz mem ddr min. frequency min. 125 125 125 mhz non-mem ddr min. frequency min. 0 0 0 mhz
3-30 dc and switching characteristics lattice semiconductor machxo 2 family data sheet notes: 1. commercial timing numbers are shown. industrial numb ers are typically slower and can be extracted from the lattice design tools. timing in range 0c to 85c shown, please consult software for timing outside this range. 2. general i/o timing numbers based on lvcmos 2.5, 8ma, 0pf load. 3. generic ddr timing numbers based on lvds i/o. 4. ddr timing numbers based on sstl25. ddr2 timing numbers based on sstl18. lpddr timing numbers based in lvcmos18. 5. 7:1 lvds (gddr71) uses the 1lvds i/o standard. 6. for generic ddrx1 mode t su = t ho = (t dve - t dva - 0.03ns)/2. figure 3-5. receiver rx.clk.aligned and mem ddr input waveforms figure 3-6. receiver rx.clk.centered waveforms parameter description device ze devices units -6 -5 -4 t dvadq input data valid after dqs input machxo2-1200 and larger devices, right side only. max. ui t dvedq input data hold after dqs input min. ui t dqvbs output dq data valid before dqs min. ui t dqvas output dq data valid after dqs min. ui f data mem ddr serial data speed max. mbps f sclk sclk frequency max. mhz f mem_ddr mem ddr frequency max. mbps min. mbps f mem_ddr2 mem ddr2 frequency max. mbps min. mbps f lpddr lpddr frequency max. mbps min. mbps t dva or t dvadq t dve or t dvedq rx.aligned rx clk input or dqs input rx data input or dq input t ho t ho t su t su rx.centered rx clk input rx data input
3-31 dc and switching characteristics lattice semiconductor machxo 2 family data sheet figure 3-7. transmitter tx.clk.aligned waveforms figure 3-8. transmitter tx.clk.centered and mem ddr output waveforms figure 3-9. gddr71 video timing waveforms tx clk output t dia tx data output t dib tx.aligned t dia t dib tx clk output or dqs output t dva or t dqvas tx data output or dq output t dvb or t dqvbs tx.centered t dva or t dqvas t dvb or t dqvbs 756 mbps data out 756 mbps clock out 125 mhz clock in 125 mhz
3-32 dc and switching characteristics lattice semiconductor machxo 2 family data sheet figure 3-10. receiver gddr71_rx. waveforms figure 3-11. transmitter gddr71_tx. waveforms
3-33 dc and switching characteristics lattice semiconductor machxo 2 family data sheet sysclock pll timing over recommended operating conditions machxo2 oscillator output frequency parameter descriptions conditions min. max. units f in input clock frequency (clki, clkfb) mhz f out output clock frequency (clkop, clkos, clkos2) mhz f out2 output frequency (clkos3) mhz f vco pll vco frequency mhz f pfd phase detector input frequency mhz ac characteristics t dt output clock duty cycle default duty cycle selected 3 % t ph 4 output phase accuracy ui t opjit 1 output clock period jitter f out > 100mhz ps f out < 100mhz uipp t sk input clock to output clock skew divider ratio = integer ps t w output clock pulse width at 90% or 10% 3 ns t lock 2 pll lock-in time s t ipjit input clock period jitter f out > 100mhz ps f out < 100mhz uipp t fbkdly external feedback delay ns t hi input clock high time 90% to 90% ns t lo input clock low time 10% to 10% ns t stable standby high to pll stable s t rst rst/resetm pulse width ns t rstrec rst recovery time t rst_div resetc/d pulse width t rstrec_div resetc/d recovery time t rotate-setup phasestep setup time t rotate_wd phasestep pulse width 1. jitter sample is taken over 10,000 samples of the primary pll output with a clean reference clock. 2. output clock is valid after t lock for pll reset and dynamic delay adjustment. 3. using lvds output buffers. 4. clkos as compared to clkop output. symbol parameter min. typ. max units f max oscillator output frequency 126.35 133 139.65 mhz t dt output clock duty cycle % t opjit output clock period jitter uipp t stable standby high to oscillator stable s
3-34 dc and switching characteristics lattice semiconductor machxo 2 family data sheet machxo2 ?z? standby mode timing machxo2 ?h? standby mode timing symbol parameter device min. typ. max units t pwrdn standby low to stop all ns t pwrup standby high to power up lcmxo2-256 s lcmxo2-640 s lcmxo2-1200 s lcmxo2-2000 s lcmxo2-4000 s lcmxo2-7000 s t wstandby standbyn pulse width all ns t wawake standbyn pulse rejection all ns t bndgapstbl standby high to bandgap stable all ns t porstbl standby high to por stable all ns t bnkctrlrstbl standby high to i/o bank controller stable all ns t i2ctostop i 2 c to standby controller stop signal all ns t spitostop spi to standby controller stop signal all ns t jtagtostop jtag to standby controller stop signal all ns symbol parameter device min. typ. max units t pwrdn standbyn low to stop all ns t pwrup standbyn high to power up lcmxo2-256 s lcmxo2-640 s lcmxo2-1200 s lcmxo2-2000 s lcmxo2-4000 s lcmxo2-7000 s t wstandby standbyn pulse width all ns t wawake standbyn pulse rejection all ns t bndgapstbl standbyn high to bandgap stable all ns t porstbl standbyn high to por stable all ns t bnkctrlrstbl standbyn high to i/o bank controller stable all ns t i2ctostop i 2 c to standby controller stop signal all ns t spitostop spi to standby controller stop signal all ns t jtagtostop jtag to standby controller stop signal all ns standby t pwrup standby mode t pwrdn t wsleepn or t wawake bg, por
3-35 dc and switching characteristics lattice semiconductor machxo 2 family data sheet flash download time 1, 2 jtag port timing specifications symbol parameter min. typ. max. units units t refresh por to device i/o active lcmxo2-256 507 s lcmxo2-640 944 s lcmxo2-1200 1727 s lcmxo2-2000 1304 s lcmxo2-4000 2289 s lcmxo2-7000 3605 s 1. assumes sysmem ebr initialized to an all zero pattern if they are used. 2. the flash download time is measured starting from the maximum voltage of por trip point. symbol parameter min. max. units f max tck [bscan] clock frequency mhz t btcp tck [bscan] clock pulse width ns t btcph tck [bscan] clock pulse width high ns t btcpl tck [bscan] clock pulse width low ns t bts tck [bscan] setup time ns t bth tck [bscan] hold time ns t btrf tck [bscan] rise/fall time mv/ns t btco tap controller falling edge of clock to output valid ns t btcodis tap controller falling edge of clock to output disabled ns t btcoen tap controller falling edge of clock to output enabled ns t btcrs bscan test capture register setup time ns t btcrh bscan test capture register hold time ns t butco bscan test update register, falling edge of clock to output valid ns t btuodis bscan test update register, falling edge of clock to output disabled ns t btupoen bscan test update register, falling edge of clock to output enabled ns
3-36 dc and switching characteristics lattice semiconductor machxo 2 family data sheet figure 3-12. jtag port timing waveforms i 2 c port timing specifications spi port timing specifications symbol parameter min. max. units f max maximum scl clock frequency mhz t hi high period of scl clock ns t sud data setup time ns t hud data hold time ns t sustart start condition setup time ns t sustop stop condition setup time ns t bf bus free time between stop and start condition mv/ns symbol parameter min. max. units f max maximum sck clock frequency mhz t hi high period of sck clock ns t sumaster setup time (ma ster mode) ns t holdmaster hold time (master mode) ns t suslave setup time (slave mode) ns t holdslave hold time (slave mode) ns t sck2out sck to out (slave mode) ns tms tdi tck tdo data to be captured from i/o data to be driven out to i/o a t a d d i l a v a t a d d i l a v a t a d d i l a v a t a d d i l a v data captured t btcph t btcpl t btcoen t btcrs t btupoen t butco t btuodis t btcrh t btco t btcodis t bts t bth t btcp
3-37 dc and switching characteristics lattice semiconductor machxo 2 family data sheet switching test conditions figure 3-13 shows the output test load used for ac testing. the specific values for resistance, capacitance, volt- age, and other test conditions are shown in table 3-5. figure 3-13. output test load, lvttl and lvcmos standards table 3-5. test fixture required components, non-terminated interfaces note: output test conditions for all other interfaces are determined by the respective standards. test condition r1 cl timing ref. vt lvttl and lvcmos settings (l -> h, h -> l) ? 0pf lvttl, lvcmos 3.3 = 1.5v ? lvcmos 2.5 = v ccio /2 ? lvcmos 1.8 = v ccio /2 ? lvcmos 1.5 = v ccio /2 ? lvcmos 1.2 = v ccio /2 ? lvttl and lvcmos 3.3 (z -> h) 188 0pf 1.5 v ol lvttl and lvcmos 3.3 (z -> l) v oh other lvcmos (z -> h) v ccio /2 v ol other lvcmos (z -> l) v ccio /2 v oh lv t t l + lv c m o s ( h - > z ) v oh - 0.15 v ol lv t t l + lv c m o s ( l - > z ) v ol - 0.15 v oh dut v t r1 cl test poi n t
www.latticesemi.com 4-1 ds1035 pinout information_01.0 november 2010 advance data sheet ds1035 ? 2010 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. signal descriptions signal name i/o descriptions general purpose p[edge] [row/column number]_[a/b/c/d] i/o [edge] indicates the edge of the device on which the pad is located. valid edge designations are l (left), b (bottom), r (right), t (top). [row/column number] indicates the pfu row or the column of the device on which the pio group exists. when edge is t (top) or (bottom), only need to specify row number. when edge is l (left) or r (right), only need to specify column number. [a/b/c/d] indicates the pio within the group to which the pad is connected. some of these user-programmable pins are sh ared with special function pins. when not used as special function pins, these pins ca n be programmed as i/os for user logic. during configuration of the user-programmable i/os, the user has an option to tri-state the ? i/os and enable an internal pull-up resistor. this option also applies to unused pins (or those not bonded to a package pin). the default during configuration is for user-programmable i/os to be tri-stated with an internal pull-down resi stor enabled. when the device is erased, i/os will be tri-stated with an internal pull-down resistor enabled. nc ? no connect. gnd ? gnd ? ground. dedicated pins. vcc ? v cc ? the power supply pins for core logic. dedicated pins. vccp ? v ccp ? the programming power supply pin. this pin powers up the programming circuitry for the on-chip flash memory. dedicated pins. vcciox ? vccio ? the power supply pins for i/o bank x. dedicated pins. pll and clock functions (used as user-programmable i/o pins when not used for pll or clock pins) [loc]_gpll[t, c]_in ? reference clock (pll) input pads: [loc] indicates location. valid designations are l (left pll) and r (right pll). t = true and c = complement. [loc]_gpll[t, c]_fb ? optional feedback (pll) input pads: [loc] indicates location. valid designations are l (left pll) and r (right pll). t = true and c = complement. pclk [n]_[2:0] ? primary clock pads. one to three clock pads per side. test and programming (dual function pins used for test access port and during sysconfig?) tms i test mode select input pin, used to control the 1149.1 state machine. tck i test clock input pin, used to clock the 1149.1 state machine. tdi i test data input pin, used to load data into the device using an 1149.1 state machine. tdo o output pin ? test data output pin used to shift data out of the device using 1149.1. jtagenb i controls behavior of tdi, tdo, tms, tck. if the device is configured to use the jtag pins (tdi, tdo, tms, tck) as general purpose i/o then: if jtagenb is low: tdi, tdo, tms and tck can function a general purpose i/o. if jtagenb is high: tdi, tdo, tms and tck function as jtag pins. for more details, refer to tn1204, machxo2 programming and configuration usage guide . configuration (dual function pins used during sysconfig) programn i initiates configuration sequence when asserted low. this pin always has an active pull-up. initn i/o open drain pin. indicates the fpga is ready to be configured. during configuration, a pull-up is enabled. done i/o open drain pin. indicates that the configur ation sequence is complete, and the start-up sequence is in progress. machxo2 family data sheet pinout information
4-2 pinout information lattice semiconductor machxo 2 family data sheet mclk/cclk i/o input configuration clock for configuring an fpga in slave spi, serial, and cpu modes. out- put configuration clock for configuring an fpga in spi, spim, and master configuration modes. sn i slave spi active low chip select input. csspin i/o master spi active low chip select output. si/sispi/io0 i/o slave spi serial data input and master spi seri al data output or master spi dual/quad read bi- directional data i/o0. so/sispiso/io1 i/o slave spi serial data output and master spi se rial data input or master spi dual/quad read bi- directional data i/o1. scl/io2 i/o slave i 2 c clock input and master i 2 c clock output and master spi quad read bi-directional data i/o2. sda/io3 i/o slave i 2 c data input and master i 2 c data output and master spi quad read bi-directional data i/o3. signal name i/o descriptions general purpose
4-3 pinout information lattice semiconductor machxo 2 family data sheet pin information summary machxo2-256 machxo2-640 64-ball ucbga 100-pin tqfp 132-ball csbga 100-pin tqfp 132-ball csbga general purpose i/o per bank bank 0 1014141920 bank 1 1214142020 bank 2 1114142020 bank 3 1214142020 bank 4 00000 bank 5 00000 total general purpose single-ended i/o 45 56 56 79 80 differential i/o per bank bank 0 577910 bank 1 6 7 7 10 10 bank 2 5 7 7 10 10 bank 3 6 7 7 10 10 bank 4 00000 bank 5 00000 total general purpose differential i/o 22 28 28 39 40 dual function i/o 2729292929 high-speed differential outputs (bank 0) 00000 high-speed differential inputs (bank 2) 00000 dqs groups (bank 1) bank 1 00000 vccio pins bank 0 22323 bank 1 22323 bank 2 22323 bank 3 23333 bank 4 00000 bank 5 00000 jtag 55555 vcc 22424 vccp 11111 gnd 8 8 10 8 10 nc 0 24 49 1 25 total count of bonded pins 64 76 83 99 107
4-4 pinout information lattice semiconductor machxo 2 family data sheet machxo2-1200 machxo2-2000 100-pin tqfp 132-ball csbga 144-pin tqfp 100-pin tqfp 132-ball csbga 144-pin tqfp 256-ball cabga 256-ball ftbga general purpose i/o per bank bank 0 1926281926285151 bank 1 2126262126285252 bank 2 2028282028285252 bank 3 202526 6 7 8 1616 bank 4 00068101616 bank 5 000810102020 total general purpose single-ended i/o 80 105 108 80 105 112 207 207 differential i/o per bank bank 0 9 1314 9 13142525 bank 1 1013131013142626 bank 2 1014141014142626 bank 3 10121333488 bank 4 00034588 bank 5 0004551010 total general purpose differential i/o 39 52 54 39 52 56 103 103 dual function i/o 31 33 33 31 33 33 33 33 high-speed differential outputs (bank 0) 4774891414 high-speed differential inputs (bank 2) 10 14 14 10 14 14 26 26 dqs groups (bank 1) bank 1 22222222 vccio pins bank 0 23323344 bank 1 23323344 bank 2 23323344 bank 3 33311111 bank 4 00011122 bank 5 00011111 jtag 55555555 vcc 24424488 vccp 11111111 gnd 8 1012 8 10122424 nc 00700300 total count of bonded pins 100 132 137 100 132 141 256 256
4-5 pinout information lattice semiconductor machxo 2 family data sheet machxo2-4000 132-ball csbga 144-pin tqfp 256-ball cabga 256-ball ftbga 332-ball cabga 484-ball ftbga general purpose i/o per bank bank 0 262851516971 bank 1 262952526868 bank 2 282952527072 bank 3 7 9 16162424 bank 4 8 10 16 16 16 16 bank 5 101020202828 total general purpose single-ended i/o 105 115 207 207 275 279 differential i/o per bank bank 0 131425253435 bank 1 131426263434 bank 2 141426263636 bank 3 34881212 bank 4 458888 bank 5 5 5 10101414 total general purpose differential i/o 35 52 56 103 103 139 dual function i/o 373737373737 high-speed differential outputs (bank 0) 8 9 18 18 18 18 high-speed differential inputs (bank 2) 14 14 26 26 35 36 dqs groups (bank 1) bank 1 222222 vccio pins bank 0 3344510 bank 1 3344510 bank 2 3344510 bank 3 111123 bank 4 112214 bank 5 111123 jtag 555555 vcc 4488812 vccp 111111 gnd 101224242448 nc 00004104 total count of bonded pins 132 144 256 256 328 380
4-6 pinout information lattice semiconductor machxo 2 family data sheet for further information for further information regarding logic signal connections for various packages please refer to the machxo2 device pinout files. machxo2-7000 144-pin tqfp 256-ball cabga 256-ball ftbga 332-ball cabga 484-ball ftbga general purpose i/o per bank bank 0 2851516983 bank 1 2952527084 bank 2 2952527084 bank 3 9 16 16 24 28 bank 4 1016161624 bank 5 1020203032 total general purpose single-ended i/os 115 207 207 279 335 differential i/o per bank bank 0 1425253441 bank 1 1426263542 bank 2 1426263542 bank 3 4 8 8 12 14 bank 4 5 8 8 8 12 bank 5 5 10 10 15 16 total general purpose differential i/o 56 103 103 139 167 dual function i/o 3737373737 high-speed differential outputs (bank 0) 9 20 20 21 21 high-speed differential inputs (bank 2) 14 26 26 35 42 dqs groups (bank 1) bank 1 22222 vccio pins bank 0 3 4 4 5 10 bank 1 3 4 4 5 10 bank 2 3 4 4 5 10 bank 3 11123 bank 4 12214 bank 5 11123 jtag 55555 vcc 488812 vccp 11111 gnd 1224242448 nc 000048 total count of bonded pins 144 256 256 332 436
4-7 pinout information lattice semiconductor machxo 2 family data sheet thermal management thermal management is recommended as part of any sound fpga design methodology. to assess the thermal characteristics of a system, lattice sp ecifies a maximum allowable junction temperature in all device data sheets. users must complete a thermal analysis of their specific design to ensure that the device and package do not exceed the junction temperature limits. refer to the thermal management document to find the device/package specific thermal values. for further information for further information regarding ther mal management, refer to the following: ? thermal management document ? tn1198, power estimation and management for machxo2 devices ? power calculator tool included with the lattice design tools, or as a standalone download from ? www.latticesemi.com/software
www.latticesemi.com 5-1 ds1035 order info_01.0 november 2010 advance data sheet ds1035 ? 2010 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. machxo2 part number description lcmxo2 ? xxxxx x x ? x xxxxxx x xx device status blank = production device es = engineering sample grade c = commercial i = industrial logic capacity 256 = 256 luts 640 = 640 luts 1200 = 1280 luts 2000 = 2112 luts 4000 = 4320 luts 7000 = 6864 luts power/performance z = low power h = high performance supply voltage c = 2.5v/3.3v e = 1.2v speed 1 = slowest 2 3 = fastest 4 = slowest 5 6 = fastest low power high performance package tg100 = 100-pin halogen-free tqfp tg144 = 144-pin halogen-free tqfp umg64 = 64-ball halogen-free ucbga (0.4 mm pitch) mg132 = 132-ball halogen-free csbga (0.5 mm pitch) bg256 = 256-ball halogen-free cabga (0.8 mm pitch) ftg256 = 256-ball halogen-free ftbga (1.0 mm pitch) bg332 = 332-ball halogen-free cabga fg484 = 484-ball halogen-free fpbga (1.0 mm pitch) device family machxo2 pld ordering information machxo2 devices have top-side markings, for commercial and industrial grades, as shown below: note: markings are abbreviated for small packages. contact your lattice sales representative for the support of wlcsp packages. lcmxo2-1200he 6mn132c datecode machxo2 machxo2 family data sheet ordering information
5-2 ordering information lattice semiconductor machxo 2 family data sheet ultra low power commercial grade devi ces, halogen free (rohs) packaging part number luts supply voltage grade package pins temp. lcmxo2-256ze-1tg100c 256 1.2v -1 halogen-free tqfp 100 com lcmxo2-256ze-2tg100c 256 1.2v -2 halogen-free tqfp 100 com lcmxo2-256ze-3tg100c 256 1.2v -3 halogen-free tqfp 100 com lcmxo2-256ze-1umg64c 256 1.2v -1 halogen-free ucbga 64 com lcmxo2-256ze-2umg64c 256 1.2v -2 halogen-free ucbga 64 com lcmxo2-256ze-3umg64c 256 1.2v -3 halogen-free ucbga 64 com lcmxo2-256ze-1mg132c 256 1.2v -1 halogen-free csbga 132 com lcmxo2-256ze-2mg132c 256 1.2v -2 halogen-free csbga 132 com lcmxo2-256ze-3mg132c 256 1.2v -3 halogen-free csbga 132 com part number luts supply voltage grade package pins temp. lcmxo2-640ze-1tg100c 640 1.2v -1 halogen-free tqfp 100 com lcmxo2-640ze-2tg100c 640 1.2v -2 halogen-free tqfp 100 com lcmxo2-640ze-3tg100c 640 1.2v -3 halogen-free tqfp 100 com lcmxo2-640ze-1mg132c 640 1.2v -1 halogen-free csbga 132 com lcmxo2-640ze-2mg132c 640 1.2v -2 halogen-free csbga 132 com lcmxo2-640ze-3mg132c 640 1.2v -3 halogen-free csbga 132 com part number luts supply voltage grade package pins temp. lcmxo2-1200ze-1tg100c 1280 1.2v -1 halogen-free tqfp 100 com lcmxo2-1200ze-2tg100c 1280 1.2v -2 halogen-free tqfp 100 com lcmxo2-1200ze-3tg100c 1280 1.2v -3 halogen-free tqfp 100 com lcmxo2-1200ze-1tg144c 1280 1.2v -1 halogen-free tqfp 144 com lcmxo2-1200ze-2tg144c 1280 1.2v -2 halogen-free tqfp 144 com lcmxo2-1200ze-3tg144c 1280 1.2v -3 halogen-free tqfp 144 com lcmxo2-1200ze-1mg132c 1280 1.2v -1 halogen-free csbga 132 com lcmxo2-1200ze-2mg132c 1280 1.2v -2 halogen-free csbga 132 com lcmxo2-1200ze-3mg132c 1280 1.2v -3 halogen-free csbga 132 com part number luts supply voltage grade package pins temp. lcmxo2-2000ze-1tg100c 2112 1.2v -1 halogen-free tqfp 100 com lcmxo2-2000ze-2tg100c 2112 1.2v -2 halogen-free tqfp 100 com lcmxo2-2000ze-3tg100c 2112 1.2v -3 halogen-free tqfp 100 com lcmxo2-2000ze-1tg144c 2112 1.2v -1 halogen-free tqfp 144 com lcmxo2-2000ze-2tg144c 2112 1.2v -2 halogen-free tqfp 144 com lcmxo2-2000ze-3tg144c 2112 1.2v -3 halogen-free tqfp 144 com lcmxo2-2000ze-1mg132c 2112 1.2v -1 halogen-free csbga 132 com lcmxo2-2000ze-2mg132c 2112 1.2v -2 halogen-free csbga 132 com lcmxo2-2000ze-3mg132c 2112 1.2v -3 halogen-free csbga 132 com
5-3 ordering information lattice semiconductor machxo 2 family data sheet lcmxo2-2000ze-1bg256c 2112 1.2v -1 halogen-free cabga 256 com lcmxo2-2000ze-2bg256c 2112 1.2v -2 halogen-free cabga 256 com lcmxo2-2000ze-3bg256c 2112 1.2v -3 halogen-free cabga 256 com lcmxo2-2000ze-1ftg256c 2112 1.2v -1 halogen-free ftbga 256 com lcmxo2-2000ze-2ftg256c 2112 1.2v -2 halogen-free ftbga 256 com lcmxo2-2000ze-3ftg256c 2112 1.2v -3 halogen-free ftbga 256 com part number luts supply voltage grade package pins temp. lcmxo2-4000ze-1tg144c 4320 1.2v -1 halogen-free tqfp 144 com lcmxo2-4000ze-2tg144c 4320 1.2v -2 halogen-free tqfp 144 com lcmxo2-4000ze-3tg144c 4320 1.2v -3 halogen-free tqfp 144 com lcmxo2-4000ze-1mg132c 4320 1.2v -1 halogen-free csbga 132 com lcmxo2-4000ze-2mg132c 4320 1.2v -2 halogen-free csbga 132 com lcmxo2-4000ze-3mg132c 4320 1.2v -3 halogen-free csbga 132 com lcmxo2-4000ze-1bg256c 4320 1.2v -1 halogen-free cabga 256 com lcmxo2-4000ze-2bg256c 4320 1.2v -2 halogen-free cabga 256 com lcmxo2-4000ze-3bg256c 4320 1.2v -3 halogen-free cabga 256 com lcmxo2-4000ze-1ftg256c 4320 1.2v -1 halogen-free ftbga 256 com lcmxo2-4000ze-2ftg256c 4320 1.2v -2 halogen-free ftbga 256 com lcmxo2-4000ze-3ftg256c 4320 1.2v -3 halogen-free ftbga 256 com lcmxo2-4000ze-1bg332c 4320 1.2v -1 halogen-free cabga 332 com lcmxo2-4000ze-2bg332c 4320 1.2v -2 halogen-free cabga 332 com lcmxo2-4000ze-3bg332c 4320 1.2v -3 halogen-free cabga 332 com lcmxo2-4000ze-1fg484c 4320 1.2v -1 halogen-free fpbga 484 com lcmxo2-4000ze-2fg484c 4320 1.2v -2 halogen-free fpbga 484 com lcmxo2-4000ze-3fg484c 4320 1.2v -3 halogen-free fpbga 484 com part number luts supply voltage grade package pins temp. lcmxo2-7000ze-1tg144c 6864 1.2v -1 halogen-free tqfp 144 com lcmxo2-7000ze-2tg144c 6864 1.2v -2 halogen-free tqfp 144 com lcmxo2-7000ze-3tg144c 6864 1.2v -3 halogen-free tqfp 144 com lcmxo2-7000ze-1bg256c 6864 1.2v -1 halogen-free cabga 256 com lcmxo2-7000ze-2bg256c 6864 1.2v -2 halogen-free cabga 256 com lcmxo2-7000ze-3bg256c 6864 1.2v -3 halogen-free cabga 256 com lcmxo2-7000ze-1ftg256c 6864 1.2v -1 halogen-free ftbga 256 com lcmxo2-7000ze-2ftg256c 6864 1.2v -2 halogen-free ftbga 256 com lcmxo2-7000ze-3ftg256c 6864 1.2v -3 halogen-free ftbga 256 com lcmxo2-7000ze-1bg332c 6864 1.2v -1 halogen-free cabga 332 com lcmxo2-7000ze-2bg332c 6864 1.2v -2 halogen-free cabga 332 com lcmxo2-7000ze-3bg332c 6864 1.2v -3 halogen-free cabga 332 com lcmxo2-7000ze-1fg484c 6864 1.2v -1 halogen-free fpbga 484 com part number luts supply voltage grade package pins temp.
5-4 ordering information lattice semiconductor machxo 2 family data sheet high-performance commercial grade devices with voltag e regulator, halogen free (rohs) packaging lcmxo2-7000ze-2fg484c 6864 1.2v -2 halogen-free fpbga 484 com lcmxo2-7000ze-3fg484c 6864 1.2v -3 halogen-free fpbga 484 com part number luts supply voltage grade package pins temp. lcmxo2-256hc-4tg100c 256 2.5v/3.3v -4 halogen-free tqfp 100 com lcmxo2-256hc-5tg100c 256 2.5v/3.3v -5 halogen-free tqfp 100 com lcmxo2-256hc-6tg100c 256 2.5v/3.3v -6 halogen-free tqfp 100 com lcmxo2-256hc-4umg64c 256 2.5v/3.3v -4 halogen-free ucbga 64 com lcmxo2-256hc-5umg64c 256 2.5v/3.3v -5 halogen-free ucbga 64 com lcmxo2-256hc-6umg64c 256 2.5v/3.3v -6 halogen-free ucbga 64 com lcmxo2-256hc-4mg132c 256 2.5v/3.3v -4 halogen-free csbga 132 com lcmxo2-256hc-5mg132c 256 2.5v/3.3v -5 halogen-free csbga 132 com lcmxo2-256hc-6mg132c 256 2.5v/3.3v -6 halogen-free csbga 132 com part number luts supply voltage grade package pins temp. lcmxo2-640hc-4tg100c 640 2.5v/3.3v -4 halogen-free tqfp 100 com lcmxo2-640hc-5tg100c 640 2.5v/3.3v -5 halogen-free tqfp 100 com lcmxo2-640hc-6tg100c 640 2.5v/3.3v -6 halogen-free tqfp 100 com lcmxo2-640hc-4mg132c 640 2.5v/3.3v -4 halogen-free csbga 132 com lcmxo2-640hc-5mg132c 640 2.5v/3.3v -5 halogen-free csbga 132 com lcmxo2-640hc-6mg132c 640 2.5v/3.3v -6 halogen-free csbga 132 com part number luts supply voltage grade package pins temp. lcmxo2-1200hc-4tg100c 1280 2.5v/3.3v -4 halogen-free tqfp 100 com lcmxo2-1200hc-5tg100c 1280 2.5v/3.3v -5 halogen-free tqfp 100 com lcmxo2-1200hc-6tg100c 1280 2.5v/3.3v -6 halogen-free tqfp 100 com lcmxo2-1200hc-4tg144c 1280 2.5v/3.3v -4 halogen-free tqfp 144 com lcmxo2-1200hc-5tg144c 1280 2.5v/3.3v -5 halogen-free tqfp 144 com lcmxo2-1200hc-6tg144c 1280 2.5v/3.3v -6 halogen-free tqfp 144 com lcmxo2-1200hc-4mg132c 1280 2.5v/3.3v -4 halogen-free csbga 132 com lcmxo2-1200hc-5mg132c 1280 2.5v/3.3v -5 halogen-free csbga 132 com lcmxo2-1200hc-6mg132c 1280 2.5v/3.3v -6 halogen-free csbga 132 com part number luts supply voltage grade package pins temp. lcmxo2-2000hc-4tg100c 2112 2.5v/3.3v -4 halogen-free tqfp 100 com lcmxo2-2000hc-5tg100c 2112 2.5v/3.3v -5 halogen-free tqfp 100 com lcmxo2-2000hc-6tg100c 2112 2.5v/3.3v -6 halogen-free tqfp 100 com lcmxo2-2000hc-4tg144c 2112 2.5v/3.3v -4 halogen-free tqfp 144 com part number luts supply voltage grade package pins temp.
5-5 ordering information lattice semiconductor machxo 2 family data sheet lcmxo2-2000hc-5tg144c 2112 2.5v/3.3v -5 halogen-free tqfp 144 com lcmxo2-2000hc-6tg144c 2112 2.5v/3.3v -6 halogen-free tqfp 144 com lcmxo2-2000hc-4mg132c 2112 2.5v/3.3v -4 halogen-free csbga 132 com lcmxo2-2000hc-5mg132c 2112 2.5v/3.3v -5 halogen-free csbga 132 com lcmxo2-2000hc-6mg132c 2112 2.5v/3.3v -6 halogen-free csbga 132 com lcmxo2-2000hc-4bg256c 2112 2.5v/3.3v -4 halogen-free cabga 256 com lcmxo2-2000hc-5bg256c 2112 2.5v/3.3v -5 halogen-free cabga 256 com lcmxo2-2000hc-6bg256c 2112 2.5v/3.3v -6 halogen-free cabga 256 com lcmxo2-2000hc-4ftg256c 2112 2.5v/3.3v -4 halogen-free ftbga 256 com lcmxo2-2000hc-5ftg256c 2112 2.5v/3.3v -5 halogen-free ftbga 256 com lcmxo2-2000hc-6ftg256c 2112 2.5v/3.3v -6 halogen-free ftbga 256 com part number luts supply voltage grade package pins temp. lcmxo2-4000hc-4tg144c 4320 2.5v/3.3v -4 halogen-free tqfp 144 com lcmxo2-4000hc-5tg144c 4320 2.5v/3.3v -5 halogen-free tqfp 144 com lcmxo2-4000hc-6tg144c 4320 2.5v/3.3v -6 halogen-free tqfp 144 com lcmxo2-4000hc-4mg132c 4320 2.5v/3.3v -4 halogen-free csbga 132 com lcmxo2-4000hc-5mg132c 4320 2.5v/3.3v -5 halogen-free csbga 132 com lcmxo2-4000hc-6mg132c 4320 2.5v/3.3v -6 halogen-free csbga 132 com lcmxo2-4000hc-4bg256c 4320 2.5v/3.3v -4 halogen-free cabga 256 com lcmxo2-4000hc-5bg256c 4320 2.5v/3.3v -5 halogen-free cabga 256 com lcmxo2-4000hc-6bg256c 4320 2.5v/3.3v -6 halogen-free cabga 256 com lcmxo2-4000hc-4ftg256c 4320 2.5v/3.3v -4 halogen-free ftbga 256 com lcmxo2-4000hc-5ftg256c 4320 2.5v/3.3v -5 halogen-free ftbga 256 com lcmxo2-4000hc-6ftg256c 4320 2.5v/3.3v -6 halogen-free ftbga 256 com lcmxo2-4000hc-4bg332c 4320 2.5v/3.3v -4 halogen-free cabga 332 com lcmxo2-4000hc-5bg332c 4320 2.5v/3.3v -5 halogen-free cabga 332 com lcmxo2-4000hc-6bg332c 4320 2.5v/3.3v -6 halogen-free cabga 332 com lcmxo2-4000hc-4fg484c 4320 2.5v/3.3v -4 halogen-free fpbga 484 com lcmxo2-4000hc-5fg484c 4320 2.5v/3.3v -5 halogen-free fpbga 484 com lcmxo2-4000hc-6fg484c 4320 2.5v/3.3v -6 halogen-free fpbga 484 com part number luts supply voltage grade package pins temp. lcmxo2-7000hc-4tg144c 6864 2.5v/3.3v -4 halogen-free tqfp 144 com lcmxo2-7000hc-5tg144c 6864 2.5v/3.3v -5 halogen-free tqfp 144 com lcmxo2-7000hc-6tg144c 6864 2.5v/3.3v -6 halogen-free tqfp 144 com lcmxo2-7000hc-4bg256c 6864 2.5v/3.3v -4 halogen-free cabga 256 com lcmxo2-7000hc-5bg256c 6864 2.5v/3.3v -5 halogen-free cabga 256 com lcmxo2-7000hc-6bg256c 6864 2.5v/3.3v -6 halogen-free cabga 256 com lcmxo2-7000hc-4ftg256c 6864 2.5v/3.3v -4 halogen-free ftbga 256 com lcmxo2-7000hc-5ftg256c 6864 2.5v/3.3v -5 halogen-free ftbga 256 com lcmxo2-7000hc-6ftg256c 6864 2.5v/3.3v -6 halogen-free ftbga 256 com lcmxo2-7000hc-4bg332c 6864 2.5v/3.3v -4 halogen-free cabga 332 com part number luts supply voltage grade package pins temp.
5-6 ordering information lattice semiconductor machxo 2 family data sheet high-performance commercial grade devices without voltag e regulator, halogen free (rohs) packaging lcmxo2-7000hc-5bg332c 6864 2.5v/3.3v -5 halogen-free cabga 332 com lcmxo2-7000hc-6bg332c 6864 2.5v/3.3v -6 halogen-free cabga 332 com lcmxo2-7000hc-4fg484c 6864 2.5v/3.3v -4 halogen-free fpbga 484 com lcmxo2-7000hc-5fg484c 6864 2.5v/3.3v -5 halogen-free fpbga 484 com lcmxo2-7000hc-6fg484c 6864 2.5v/3.3v -6 halogen-free fpbga 484 com part number luts supply voltage grade package pins temp. lcmxo2-2000he-4tg100c 2112 1.2v -4 halogen-free tqfp 100 com lcmxo2-2000he-5tg100c 2112 1.2v -5 halogen-free tqfp 100 com lcmxo2-2000he-6tg100c 2112 1.2v -6 halogen-free tqfp 100 com lcmxo2-2000he-4tg144c 2112 1.2v -4 halogen-free tqfp 144 com lcmxo2-2000he-5tg144c 2112 1.2v -5 halogen-free tqfp 144 com lcmxo2-2000he-6tg144c 2112 1.2v -6 halogen-free tqfp 144 com lcmxo2-2000he-4mg132c 2112 1.2v -4 halogen-free csbga 132 com lcmxo2-2000he-5mg132c 2112 1.2v -5 halogen-free csbga 132 com lcmxo2-2000he-6mg132c 2112 1.2v -6 halogen-free csbga 132 com lcmxo2-2000he-4bg256c 2112 1.2v -4 halogen-free cabga 256 com lcmxo2-2000he-5bg256c 2112 1.2v -5 halogen-free cabga 256 com lcmxo2-2000he-6bg256c 2112 1.2v -6 halogen-free cabga 256 com lcmxo2-2000he-4ftg256c 2112 1.2v -4 halogen-free ftbga 256 com lcmxo2-2000he-5ftg256c 2112 1.2v -5 halogen-free ftbga 256 com lcmxo2-2000he-6ftg256c 2112 1.2v -6 halogen-free ftbga 256 com part number luts supply voltage grade package pins temp. lcmxo2-4000he-4tg144c 4320 1.2v -4 halogen-free tqfp 144 com lcmxo2-4000he-5tg144c 4320 1.2v -5 halogen-free tqfp 144 com lcmxo2-4000he-6tg144c 4320 1.2v -6 halogen-free tqfp 144 com lcmxo2-4000he-4mg132c 4320 1.2v -4 halogen-free csbga 132 com lcmxo2-4000he-5mg132c 4320 1.2v -5 halogen-free csbga 132 com lcmxo2-4000he-6mg132c 4320 1.2v -6 halogen-free csbga 132 com lcmxo2-4000he-4bg256c 4320 1.2v -4 halogen-free cabga 256 com lcmxo2-4000he-5bg256c 4320 1.2v -5 halogen-free cabga 256 com lcmxo2-4000he-6bg256c 4320 1.2v -6 halogen-free cabga 256 com lcmxo2-4000he-4ftg256c 4320 1.2v -4 halogen-free ftbga 256 com lcmxo2-4000he-5ftg256c 4320 1.2v -5 halogen-free ftbga 256 com lcmxo2-4000he-6ftg256c 4320 1.2v -6 halogen-free ftbga 256 com lcmxo2-4000he-4bg332c 4320 1.2v -4 halogen-free cabga 332 com lcmxo2-4000he-5bg332c 4320 1.2v -5 halogen-free cabga 332 com lcmxo2-4000he-6bg332c 4320 1.2v -6 halogen-free cabga 332 com lcmxo2-4000he-4fg484c 4320 1.2v -4 halogen-free fpbga 484 com part number luts supply voltage grade package pins temp.
5-7 ordering information lattice semiconductor machxo 2 family data sheet ultra low power industrial grade devices, haloge n free (rohs) packaging l lcmxo2-4000he-5fg484c 4320 1.2v -5 halogen-free fpbga 484 com lcmxo2-4000he-6fg484c 4320 1.2v -6 halogen-free fpbga 484 com part number luts supply voltage grade package pins temp. lcmxo2-7000he-4tg144c 6864 1.2v -4 halogen-free tqfp 144 com lcmxo2-7000he-5tg144c 6864 1.2v -5 halogen-free tqfp 144 com lcmxo2-7000he-6tg144c 6864 1.2v -6 halogen-free tqfp 144 com lcmxo2-7000he-4bg256c 6864 1.2v -4 halogen-free cabga 256 com lcmxo2-7000he-5bg256c 6864 1.2v -5 halogen-free cabga 256 com lcmxo2-7000he-6bg256c 6864 1.2v -6 halogen-free cabga 256 com lcmxo2-7000he-4ftg256c 6864 1.2v -4 halogen-free ftbga 256 com lcmxo2-7000he-5ftg256c 6864 1.2v -5 halogen-free ftbga 256 com lcmxo2-7000he-6ftg256c 6864 1.2v -6 halogen-free ftbga 256 com lcmxo2-7000he-4bg332c 6864 1.2v -4 halogen-free cabga 332 com lcmxo2-7000he-5bg332c 6864 1.2v -5 halogen-free cabga 332 com lcmxo2-7000he-6bg332c 6864 1.2v -6 halogen-free cabga 332 com lcmxo2-7000he-4fg484c 6864 1.2v -4 halogen-free fpbga 484 com lcmxo2-7000he-5fg484c 6864 1.2v -5 halogen-free fpbga 484 com lcmxo2-7000he-6fg484c 6864 1.2v -6 halogen-free fpbga 484 com part number luts supply voltage grade package pins temp. lcmxo2-256ze-1tg100i 256 1.2v -1 halogen-free tqfp 100 ind lcmxo2-256ze-2tg100i 256 1.2v -2 halogen-free tqfp 100 ind lcmxo2-256ze-3tg100i 256 1.2v -3 halogen-free tqfp 100 ind lcmxo2-256ze-1umg64i 256 1.2v -1 halogen-free ucbga 64 ind lcmxo2-256ze-2umg64i 256 1.2v -2 halogen-free ucbga 64 ind lcmxo2-256ze-3umg64i 256 1.2v -3 halogen-free ucbga 64 ind lcmxo2-256ze-1mg132i 256 1.2v -1 halogen-free csbga 132 ind lcmxo2-256ze-2mg132i 256 1.2v -2 halogen-free csbga 132 ind lcmxo2-256ze-3mg132i 256 1.2v -3 halogen-free csbga 132 ind part number luts supply voltage grade package pins temp. lcmxo2-640ze-1tg100i 640 1.2v -1 halogen-free tqfp 100 ind lcmxo2-640ze-2tg100i 640 1.2v -2 halogen-free tqfp 100 ind lcmxo2-640ze-3tg100i 640 1.2v -3 halogen-free tqfp 100 ind lcmxo2-640ze-1mg132i 640 1.2v -1 halogen-free csbga 132 ind lcmxo2-640ze-2mg132i 640 1.2v -2 halogen-free csbga 132 ind lcmxo2-640ze-3mg132i 640 1.2v -3 halogen-free csbga 132 ind part number luts supply voltage grade package pins temp.
5-8 ordering information lattice semiconductor machxo 2 family data sheet part number luts supply voltage grade package pins temp. lcmxo2-1200ze-1tg100i 1280 1.2v -1 halogen-free tqfp 100 ind lcmxo2-1200ze-2tg100i 1280 1.2v -2 halogen-free tqfp 100 ind lcmxo2-1200ze-3tg100i 1280 1.2v -3 halogen-free tqfp 100 ind lcmxo2-1200ze-1tg144i 1280 1.2v -1 halogen-free tqfp 144 ind lcmxo2-1200ze-2tg144i 1280 1.2v -2 halogen-free tqfp 144 ind lcmxo2-1200ze-3tg144i 1280 1.2v -3 halogen-free tqfp 144 ind lcmxo2-1200ze-1mg132i 1280 1.2v -1 halogen-free csbga 132 ind lcmxo2-1200ze-2mg132i 1280 1.2v -2 halogen-free csbga 132 ind lcmxo2-1200ze-3mg132i 1280 1.2v -3 halogen-free csbga 132 ind part number luts supply voltage grade package pins temp. lcmxo2-2000ze-1tg100i 2112 1.2v -1 halogen-free tqfp 100 ind lcmxo2-2000ze-2tg100i 2112 1.2v -2 halogen-free tqfp 100 ind lcmxo2-2000ze-3tg100i 2112 1.2v -3 halogen-free tqfp 100 ind lcmxo2-2000ze-1tg144i 2112 1.2v -1 halogen-free tqfp 144 ind lcmxo2-2000ze-2tg144i 2112 1.2v -2 halogen-free tqfp 144 ind lcmxo2-2000ze-3tg144i 2112 1.2v -3 halogen-free tqfp 144 ind lcmxo2-2000ze-1mg132i 2112 1.2v -1 halogen-free csbga 132 ind lcmxo2-2000ze-2mg132i 2112 1.2v -2 halogen-free csbga 132 ind lcmxo2-2000ze-3mg132i 2112 1.2v -3 halogen-free csbga 132 ind lcmxo2-2000ze-1bg256i 2112 1.2v -1 halogen-free cabga 256 ind lcmxo2-2000ze-2bg256i 2112 1.2v -2 halogen-free cabga 256 ind lcmxo2-2000ze-3bg256i 2112 1.2v -3 halogen-free cabga 256 ind lcmxo2-2000ze-1ftg256i 2112 1.2v -1 halogen-free ftbga 256 ind lcmxo2-2000ze-2ftg256i 2112 1.2v -2 halogen-free ftbga 256 ind lcmxo2-2000ze-3ftg256i 2112 1.2v -3 halogen-free ftbga 256 ind part number luts supply voltage grade package pins temp. lcmxo2-4000ze-1tg144i 4320 1.2v -1 halogen-free tqfp 144 ind lcmxo2-4000ze-2tg144i 4320 1.2v -2 halogen-free tqfp 144 ind lcmxo2-4000ze-3tg144i 4320 1.2v -3 halogen-free tqfp 144 ind lcmxo2-4000ze-1mg132i 4320 1.2v -1 halogen-free csbga 132 ind lcmxo2-4000ze-2mg132i 4320 1.2v -2 halogen-free csbga 132 ind lcmxo2-4000ze-3mg132i 4320 1.2v -3 halogen-free csbga 132 ind lcmxo2-4000ze-1bg256i 4320 1.2v -1 halogen-free cabga 256 ind lcmxo2-4000ze-2bg256i 4320 1.2v -2 halogen-free cabga 256 ind lcmxo2-4000ze-3bg256i 4320 1.2v -3 halogen-free cabga 256 ind lcmxo2-4000ze-1ftg256i 4320 1.2v -1 halogen-free ftbga 256 ind lcmxo2-4000ze-2ftg256i 4320 1.2v -2 halogen-free ftbga 256 ind lcmxo2-4000ze-3ftg256i 4320 1.2v -3 halogen-free ftbga 256 ind lcmxo2-4000ze-1bg332i 4320 1.2v -1 halogen-free cabga 332 ind
5-9 ordering information lattice semiconductor machxo 2 family data sheet high-performance industrial gr ade devices with voltage regul ator, halogen free (rohs) packaging lcmxo2-4000ze-2bg332i 4320 1.2v -2 halogen-free cabga 332 ind lcmxo2-4000ze-3bg332i 4320 1.2v -3 halogen-free cabga 332 ind lcmxo2-4000ze-1fg484i 4320 1.2v -1 halogen-free fpbga 484 ind lcmxo2-4000ze-2fg484i 4320 1.2v -2 halogen-free fpbga 484 ind lcmxo2-4000ze-3fg484i 4320 1.2v -3 halogen-free fpbga 484 ind part number luts supply voltage grade package pins temp. lcmxo2-7000ze-1tg144i 6864 1.2v -1 halogen-free tqfp 144 ind lcmxo2-7000ze-2tg144i 6864 1.2v -2 halogen-free tqfp 144 ind lcmxo2-7000ze-3tg144i 6864 1.2v -3 halogen-free tqfp 144 ind lcmxo2-7000ze-1bg256i 6864 1.2v -1 halogen-free cabga 256 ind lcmxo2-7000ze-2bg256i 6864 1.2v -2 halogen-free cabga 256 ind lcmxo2-7000ze-3bg256i 6864 1.2v -3 halogen-free cabga 256 ind lcmxo2-7000ze-1ftg256i 6864 1.2v -1 halogen-free ftbga 256 ind lcmxo2-7000ze-2ftg256i 6864 1.2v -2 halogen-free ftbga 256 ind lcmxo2-7000ze-3ftg256i 6864 1.2v -3 halogen-free ftbga 256 ind lcmxo2-7000ze-1bg332i 6864 1.2v -1 halogen-free cabga 332 ind lcmxo2-7000ze-2bg332i 6864 1.2v -2 halogen-free cabga 332 ind lcmxo2-7000ze-3bg332i 6864 1.2v -3 halogen-free cabga 332 ind lcmxo2-7000ze-1fg484i 6864 1.2v -1 halogen-free fpbga 484 ind lcmxo2-7000ze-2fg484i 6864 1.2v -2 halogen-free fpbga 484 ind lcmxo2-7000ze-3fg484i 6864 1.2v -3 halogen-free fpbga 484 ind part number luts supply voltage grade package pins temp. lcmxo2-256hc-4tg100i 256 2.5v/3.3v -4 halogen-free tqfp 100 ind lcmxo2-256hc-5tg100i 256 2.5v/3.3v -5 halogen-free tqfp 100 ind lcmxo2-256hc-6tg100i 256 2.5v/3.3v -6 halogen-free tqfp 100 ind lcmxo2-256hc-4umg64i 256 2.5v/3.3v -4 halogen-free ucbga 64 ind lcmxo2-256hc-5umg64i 256 2.5v/3.3v -5 halogen-free ucbga 64 ind lcmxo2-256hc-6umg64i 256 2.5v /3.3v -6 halogen-free ucbga 64 ind lcmxo2-256hc-4mg132i 256 2.5v/3.3v -4 halogen-free csbga 132 ind lcmxo2-256hc-5mg132i 256 2.5v/3.3v -5 halogen-free csbga 132 ind lcmxo2-256hc-6mg132i 256 2.5v/3.3v -6 halogen-free csbga 132 ind part number luts supply voltage grade package pins temp. lcmxo2-640hc-4tg100i 640 2.5v/3 .3v -4 halogen-free tqfp 100 ind lcmxo2-640hc-5tg100i 640 2.5v/3 .3v -5 halogen-free tqfp 100 ind lcmxo2-640hc-6tg100i 640 2.5v/3 .3v -6 halogen-free tqfp 100 ind lcmxo2-640hc-4mg132i 640 2.5v/3.3v -4 halogen-free csbga 132 ind part number luts supply voltage grade package pins temp.
5-10 ordering information lattice semiconductor machxo 2 family data sheet lcmxo2-640hc-5mg132i 640 2.5v/3.3v -5 halogen-free csbga 132 ind lcmxo2-640hc-6mg132i 640 2.5v/3.3v -6 halogen-free csbga 132 ind part number luts supply voltage grade package pins temp. lcmxo2-1200hc-4tg100i 1280 2.5v/3.3v -4 halogen-free tqfp 100 ind lcmxo2-1200hc-5tg100i 1280 2.5v/3.3v -5 halogen-free tqfp 100 ind lcmxo2-1200hc-6tg100i 1280 2.5v/3.3v -6 halogen-free tqfp 100 ind lcmxo2-1200hc-4tg144i 1280 2.5v/3.3v -4 halogen-free tqfp 144 ind lcmxo2-1200hc-5tg144i 1280 2.5v/3.3v -5 halogen-free tqfp 144 ind lcmxo2-1200hc-6tg144i 1280 2.5v/3.3v -6 halogen-free tqfp 144 ind lcmxo2-1200hc-4mg132i 1280 2.5v/3.3v -4 halogen-free csbga 132 ind lcmxo2-1200hc-5mg132i 1280 2.5v/3.3v -5 halogen-free csbga 132 ind lcmxo2-1200hc-6mg132i 1280 2.5v/3.3v -6 halogen-free csbga 132 ind part number luts supply voltage grade package pins temp. lcmxo2-2000hc-4tg100i 2112 2.5v/3.3v -4 halogen-free tqfp 100 ind lcmxo2-2000hc-5tg100i 2112 2.5v/3.3v -5 halogen-free tqfp 100 ind lcmxo2-2000hc-6tg100i 2112 2.5v/3.3v -6 halogen-free tqfp 100 ind lcmxo2-2000hc-4tg144i 2112 2.5v/3.3v -4 halogen-free tqfp 144 ind lcmxo2-2000hc-5tg144i 2112 2.5v/3.3v -5 halogen-free tqfp 144 ind lcmxo2-2000hc-6tg144i 2112 2.5v/3.3v -6 halogen-free tqfp 144 ind lcmxo2-2000hc-4mg132i 2112 2.5v/3.3v -4 halogen-free csbga 132 ind lcmxo2-2000hc-5mg132i 2112 2.5v/3.3v -5 halogen-free csbga 132 ind lcmxo2-2000hc-6mg132i 2112 2.5v/3.3v -6 halogen-free csbga 132 ind lcmxo2-2000hc-4bg256i 2112 2.5v/3.3v -4 halogen-free cabga 256 ind lcmxo2-2000hc-5bg256i 2112 2.5v/3.3v -5 halogen-free cabga 256 ind lcmxo2-2000hc-6bg256i 2112 2.5v/3.3v -6 halogen-free cabga 256 ind lcmxo2-2000hc-4ftg256i 2112 2.5v/3.3v -4 halogen-free ftbga 256 ind lcmxo2-2000hc-5ftg256i 2112 2.5v/3.3v -5 halogen-free ftbga 256 ind lcmxo2-2000hc-6ftg256i 2112 2.5v/3.3v -6 halogen-free ftbga 256 ind part number luts supply voltage grade package pins temp. lcmxo2-4000hc-4tg144i 4320 2.5v/3.3v -4 halogen-free tqfp 144 ind lcmxo2-4000hc-5tg144i 4320 2.5v/3.3v -5 halogen-free tqfp 144 ind lcmxo2-4000hc-6tg144i 4320 2.5v/3.3v -6 halogen-free tqfp 144 ind lcmxo2-4000hc-4mg132i 4320 2.5v/3.3v -4 halogen-free csbga 132 ind lcmxo2-4000hc-5mg132i 4320 2.5v/3.3v -5 halogen-free csbga 132 ind lcmxo2-4000hc-6mg132i 4320 2.5v/3.3v -6 halogen-free csbga 132 ind lcmxo2-4000hc-4bg256i 4320 2.5v/3.3v -4 halogen-free cabga 256 ind lcmxo2-4000hc-5bg256i 4320 2.5v/3.3v -5 halogen-free cabga 256 ind lcmxo2-4000hc-6bg256i 4320 2.5v/3.3v -6 halogen-free cabga 256 ind part number luts supply voltage grade package pins temp.
5-11 ordering information lattice semiconductor machxo 2 family data sheet high performance industrial grade devices without voltag e regulator, halogen free (rohs) packaging lcmxo2-4000hc-4ftg256i 4320 2.5v/3.3v -4 halogen-free ftbga 256 ind lcmxo2-4000hc-5ftg256i 4320 2.5v/3.3v -5 halogen-free ftbga 256 ind lcmxo2-4000hc-6ftg256i 4320 2.5v/3.3v -6 halogen-free ftbga 256 ind lcmxo2-4000hc-4bg332i 4320 2.5v/3.3v -4 halogen-free cabga 332 ind lcmxo2-4000hc-5bg332i 4320 2.5v/3.3v -5 halogen-free cabga 332 ind lcmxo2-4000hc-6bg332i 4320 2.5v/3.3v -6 halogen-free cabga 332 ind lcmxo2-4000hc-4fg484i 4320 2.5v/3.3v -4 halogen-free fpbga 484 ind lcmxo2-4000hc-5fg484i 4320 2.5v/3.3v -5 halogen-free fpbga 484 ind lcmxo2-4000hc-6fg484i 4320 2.5v/3.3v -6 halogen-free fpbga 484 ind part number luts supply voltage grade package pins temp. lcmxo2-7000hc-4tg144i 6864 2.5v/3.3v -4 halogen-free tqfp 144 ind lcmxo2-7000hc-5tg144i 6864 2.5v/3.3v -5 halogen-free tqfp 144 ind lcmxo2-7000hc-6tg144i 6864 2.5v/3.3v -6 halogen-free tqfp 144 ind lcmxo2-7000hc-4bg256i 6864 2.5v/3.3v -4 halogen-free cabga 256 ind lcmxo2-7000hc-5bg256i 6864 2.5v/3.3v -5 halogen-free cabga 256 ind lcmxo2-7000hc-6bg256i 6864 2.5v/3.3v -6 halogen-free cabga 256 ind lcmxo2-7000hc-4ftg256i 6864 2.5v/3.3v -4 halogen-free ftbga 256 ind lcmxo2-7000hc-5ftg256i 6864 2.5v/3.3v -5 halogen-free ftbga 256 ind lcmxo2-7000hc-6ftg256i 6864 2.5v/3.3v -6 halogen-free ftbga 256 ind lcmxo2-7000hc-4bg332i 6864 2.5v/3.3v -4 halogen-free cabga 332 ind lcmxo2-7000hc-5bg332i 6864 2.5v/3.3v -5 halogen-free cabga 332 ind lcmxo2-7000hc-6bg332i 6864 2.5v/3.3v -6 halogen-free cabga 332 ind lcmxo2-7000hc-4fg484i 6864 2.5v/3.3v -4 halogen-free fpbga 484 ind lcmxo2-7000hc-5fg484i 6864 2.5v/3.3v -5 halogen-free fpbga 484 ind lcmxo2-7000hc-6fg484i 6864 2.5v/3.3v -6 halogen-free fpbga 484 ind part number luts supply voltage grade package pins temp. lcmxo2-2000he-4tg100i 2112 1.2v -4 halogen-free tqfp 100 ind lcmxo2-2000he-5tg100i 2112 1.2v -5 halogen-free tqfp 100 ind lcmxo2-2000he-6tg100i 2112 1.2v -6 halogen-free tqfp 100 ind lcmxo2-2000he-4tg144i 2112 1.2v -4 halogen-free tqfp 144 ind lcmxo2-2000he-5tg144i 2112 1.2v -5 halogen-free tqfp 144 ind lcmxo2-2000he-6tg144i 2112 1.2v -6 halogen-free tqfp 144 ind lcmxo2-2000he-4mg132i 2112 1.2v -4 halogen-free csbga 132 ind lcmxo2-2000he-5mg132i 2112 1.2v -5 halogen-free csbga 132 ind lcmxo2-2000he-6mg132i 2112 1.2v -6 halogen-free csbga 132 ind lcmxo2-2000he-4bg256i 2112 1.2v -4 halogen-free cabga 256 ind lcmxo2-2000he-5bg256i 2112 1.2v -5 halogen-free cabga 256 ind lcmxo2-2000he-6bg256i 2112 1.2v -6 halogen-free cabga 256 ind part number luts supply voltage grade package pins temp.
5-12 ordering information lattice semiconductor machxo 2 family data sheet lcmxo2-2000he-4ftg256i 2112 1.2v -4 halogen-free ftbga 256 ind lcmxo2-2000he-5ftg256i 2112 1.2v -5 halogen-free ftbga 256 ind lcmxo2-2000he-6ftg256i 2112 1.2v -6 halogen-free ftbga 256 ind part number luts supply voltage grade package pins temp. lcmxo2-4000he-4tg144i 4320 1.2v -4 halogen-free tqfp 144 ind lcmxo2-4000he-5tg144i 4320 1.2v -5 halogen-free tqfp 144 ind lcmxo2-4000he-6tg144i 4320 1.2v -6 halogen-free tqfp 144 ind lcmxo2-4000he-4mg132i 4320 1.2v -4 halogen-free csbga 132 ind lcmxo2-4000he-5mg132i 4320 1.2v -5 halogen-free csbga 132 ind lcmxo2-4000he-6mg132i 4320 1.2v -6 halogen-free csbga 132 ind lcmxo2-4000he-4bg256i 4320 1.2v -4 halogen-free cabga 256 ind lcmxo2-4000he-5bg256i 4320 1.2v -5 halogen-free cabga 256 ind lcmxo2-4000he-6bg256i 4320 1.2v -6 halogen-free cabga 256 ind lcmxo2-4000he-4ftg256i 4320 1.2v -4 halogen-free ftbga 256 ind lcmxo2-4000he-5ftg256i 4320 1.2v -5 halogen-free ftbga 256 ind lcmxo2-4000he-6ftg256i 4320 1.2v -6 halogen-free ftbga 256 ind lcmxo2-4000he-4bg332i 4320 1.2v -4 halogen-free cabga 332 ind lcmxo2-4000he-5bg332i 4320 1.2v -5 halogen-free cabga 332 ind lcmxo2-4000he-6bg332i 4320 1.2v -6 halogen-free cabga 332 ind lcmxo2-4000he-4fg484i 4320 1.2v -4 halogen-free fpbga 484 ind lcmxo2-4000he-5fg484i 4320 1.2v -5 halogen-free fpbga 484 ind lcmxo2-4000he-6fg484i 4320 1.2v -6 halogen-free fpbga 484 ind part number luts supply voltage grade package pins temp. lcmxo2-7000he-4tg144i 6864 1.2v -4 halogen-free tqfp 144 ind lcmxo2-7000he-5tg144i 6864 1.2v -5 halogen-free tqfp 144 ind lcmxo2-7000he-6tg144i 6864 1.2v -6 halogen-free tqfp 144 ind lcmxo2-7000he-4bg256i 6864 1.2v -4 halogen-free cabga 256 ind lcmxo2-7000he-5bg256i 6864 1.2v -5 halogen-free cabga 256 ind lcmxo2-7000he-6bg256i 6864 1.2v -6 halogen-free cabga 256 ind lcmxo2-7000he-4ftg256i 6864 1.2v -4 halogen-free ftbga 256 ind lcmxo2-7000he-5ftg256i 6864 1.2v -5 halogen-free ftbga 256 ind lcmxo2-7000he-6ftg256i 6864 1.2v -6 halogen-free ftbga 256 ind lcmxo2-7000he-4bg332i 6864 1.2v -4 halogen-free cabga 332 ind lcmxo2-7000he-5bg332i 6864 1.2v -5 halogen-free cabga 332 ind lcmxo2-7000he-6bg332i 6864 1.2v -6 halogen-free cabga 332 ind lcmxo2-7000he-4fg484i 6864 1.2v -4 halogen-free fpbga 484 ind lcmxo2-7000he-5fg484i 6864 1.2v -5 halogen-free fpbga 484 ind lcmxo2-7000he-6fg484i 6864 1.2v -6 halogen-free fpbga 484 ind part number luts supply voltage grade package pins temp.
november 2010 advance data sheet ds1035 ? 2010 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. www.latticesemi.com 6-1 ds1035 further info_01.0 for further information a variety of technical notes for the machxo2 family are available on the lattice web site. ? tn1198, power estimation and management for machxo2 devices ? tn1199, machxo2 sysclock pll design and usage guide ? tn1200, machxo2 density migration ? tn1201, memory usage guide for machxo2 devices ? tn1202, machxo2 sysio usage guide ? tn1203, implementing high-speed interfaces with machxo2 devices ? tn1204, machxo2 programming and configuration usage guide ? tn1205, using user flash memory and hardened control functions in machxo2 devices ? tn1206, machxo2 sed usage guide ? tn1207, using traceid in machxo2 devices ? tn1074, pcb layout recommendations for bga packages ? tn1087, minimizing system interruption during configuration using transfr technology ? an8066, boundary scan testability wi th lattice sysio capability ? machxo2 device pinout files ? thermal management document ? lattice design tools ? stand-alone power calculator for machxo2 devices for further information on interface standards, refer to the following web sites: ? jedec standards (lvttl, lvcmos, lv ds, ddr, ddr2, lpddr): www.jedec.org ? pci: www.pcisig.com machxo2 family data sheet supplemental information
november 2010 advance data sheet ds1035 ? 2010 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. www.latticesemi.com 7-1 ds1035 revision history date version section change summary november 2010 01.0 ? initial release. machxo2 family data sheet revision history

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